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never stop thinking. microcontrollers data sheet, v0.3, sep. 2003 tc1130 32-bit single-chip microcontroller pr el i m i n ar y
edition 2003-09 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certai n components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but no t limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms a nd conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in lif e-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
microcontrollers data sheet, v0.3, sep. 2003 never stop thinking. tc1130 32-bit single-chip microcontroller
tc1130 advance information revision history: 2003-09 v0.3 previous version: page subjects (major changes since last revision) we listen to your comments any information within this do cument that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to th is document) to: mcdocu.comments@infineon.com
data sheet 1 v0.3, 2003-09 tc1130 32-bit single-chip microcontroller tricore family advance information ? high performance 32-bit tricore v1.3 cpu with 4-stage pipeline floating point unit (fpu) dual issue super-sca lar implementation ? mac instruction maximum triple issue circular buffer and bit-reverse ad dressing modes for dsp algorithms flexible multi-master interrupt system very fast interrupt response time hardware controlled context swit ch for task switch and interrupts memory management unit (mmu) on-chip memory ? 32 kbyte data memory (spram) ? 32 kbyte code memory (spram) ? 16 kbyte instruction cache (icache). ? 64kbyte sram data memory unit (dmu) ? 16 kbyte boot rom on-chip bus systems ? 64-bit high performance local memory bu s (lmb) for fast a ccess between caches and on-local memories and fpi interface ? on-chip flexible peripheral interconne ct buses (fpi) for interconnections of functional units dma controller with 8 channe ls for data transfer operatio ns between peripheral units and memory locations ? two high speed micro link interfaces (mli0/1) for controll er communication and emulation flexible external bus in terface unit (ebu) to a ccess external data memories one multifunctional general purpose time r units (gptu) with three 32-bit timer/ counters two capture and compare units (ccu60/1 ) for pwm signal generation, each with ? 3-channel, 16 bit c apture and compare unit ? 1-channel, 16 bit compare unit three asynchronous/synchronous serial channels (asc0/1/2) with baudrate generator, parity, framing a nd overrun error detection, s upport fifo and irda data transmission two high speed synchronous serial ch annels (ssc0/1) with programmable data length, fifo support and shift direction one multican module with four can n odes and 64 message buffers for high efficiency data handling fast ethernet controller with 10/100 mbps mii-ba sed physical devices support
tc1130 data sheet 2 v0.3, 2003-09 usb module with comp liance to usb specif ication revision 1.1, with support for 1.5mbaud to 12mbaud devices inter-ic (iic) module with two physical iic buses digital i/o ports with 3.3v io capabilities level 2 on-chip debug support power management system clock generation unit with pll maximum cpu and bus clock frequency at 150mhz without mmu and 120mhz with mmu ambient temperature under bias: -40 to +85c p-lbga-208 package
tc1130 data sheet 3 v0.3, 2003-09 block diagram figure 1 tc1130 block diagram ce da r_ b lk bo ot- r om 16 k bytes as c0 fi f o, irda as c1 fifo, ir da asc2 fifo, irda s sc0 ssc1 ii c 2 chan nel s scu (p wr) p owe r man agem ent, watchd og t i m er, reset s bcu fp i b us cerb er us jtag p ll tricore 1m cpu fp u ocds pmi (p rogram mem or y in ter face ) 32 kb s cr atch p ad ra m 16 k b inst ruction cache dm u 64 k b s ram jtag i/ o x tal2 x tal1 5 c ontrol br kout brkin 7 ocds 2 16 2 dm i (dat a m emor y in ter face) 32 kb scr atch pad ra m lbcu lmb bus lf i bri dge 2 2 2 8 3 4 p ort 0 p ort 1 p ort 2 m dio txclk rxclk 15 por t3 por t4 m m u lm b (lo cal m em ory b us) 64 bit exter nal i nterr upts 128 64 v dd 1.5-3.3 v v ss tc113 0 b l ock diag ra m s tm us b ethe rne t m u ltican 4 no des d ma 8 chan nel s gp tu 3 t im ers ccu6 ccu61 ccu 60 mli 1 m li0 m em che cker 2 8 411 2 2 13 16 16 16 16 8 8 3 6 3 3 7 8 8 8 d+ d- cps ebu 32 23 ad[31: 0] eb u_ contro l 24 a [2 3:0] 3 1 1 1 1 1 fpi bus ( flex ible per iph eral inte rfa ce), 32 bit d ma b us, 32 b it s mif
tc1130 data sheet 4 v0.3, 2003-09 logic symbol figure 2 tc1130 logic symbol mcb04945mo d po rt 0 1 6 -bit wai t rd/wr rd hwcfg[0:2] nmi hdrst porst v ss v ddosc3 ras al e ebu co n t ro l alternate functions digital circuitry po we r su p p ly 3 general control cas cs[0:3] 4 cscomb sdcl ki cke mr / w bfcl ki baa adv sdcl ko mi i _ txc l k mi i _ r xc l k mi i _ md i o d+ xtal 1 xtal 2 ethernet clock v ssosc3 oscillator 14 6 v dd v ddp 9 tdi tck trst a[0:23] bc[0:3] ad[0:31] po rt 1 1 6 -bit po rt 2 1 6 -bit po rt 3 1 6 -bit po rt 4 8 -bit gptu, mu lt ican, ssc0 / 1 , asc1/2, ccu60, mli0, ebu, scu, external interrupts ssc0/1, multican, ethernet, ebu, scu, ocds asc0/1/2, ssc0/1, iic, ccu6 0 , ebu, scu ssc0/1, ccu61, mli1, ocds tdo ocds / jtag control usb, mli0, scu bfcl ko tc1130 tms brki n trclk d- usb v ddosc v ssosc 4
tc1130 data sheet 5 v0.3, 2003-09 pin configuration figure 3 tc1130 pinning : p-bga-208 package (top view) mcp04950mod abcdefg hj p2 . 7 klmn v dd os c3 pr v ss t reser ved p3 . 1 0 16 15 p0 . 9 p0 . 1 14 p1 . 1 0 16 15 14 13 v ss 13 12 11 10 9 8 7 6 5 4 3 2 1 11 1 0 9 8 7 6 5 4 3 2 1 1 2 reser ved reser ved abcd efghj klmn pr t v ss v dd v dd v dd v ss v ss v dd v dd v dd v ss v ss v dd v ss v ss v dd p3 . 1 1 p3 . 1 2 p2 . 1 5 p2 . 1 4 p2 . 1 1 p2 . 9 p2 . 8 v ddosc xtal 1 xtal 2 d- p2 . 4 p0 . 3 v ss p2 . 1 2 p3 . 1 5 p3 . 9 p3 . 5 p3 . 6 p3 . 3 p3 . 2 p3 . 8 p3 . 0 p3 . 1 p1 . 9 p1 . 1 1 p1 . 1 4 p1 . 1 3 p1 . 1 5 p3 . 4 p3 . 7 p3 . 1 4 p2 . 1 3 hw cf g 1 hw cf g 0 p2 . 5 p2 . 3 p0 . 1 0 d+ td i p0 . 8 p2 . 2 v ddp v ss p2 . 1 0 p3 . 1 3 v ddp v ss v dd p1 . 1 2 v ddp p1 . 8 p1 . 7 p1 . 5 p1 . 6 p1 . 3 p1 . 1 p1 . 2 baa adv p1 . 4 p1 . 0 a1 7 a1 8 a1 9 a2 0 a1 6 wai t cs2 cs0 cs1 ad0 cs3 a1 5 bc 3 ad 1 bc 2 ad 1 6 bc 1 ad 2 ad 3 ras bc 0 ad 1 7 ad 4 cas ad 1 8 ad 1 9 ad 2 0 v ddp ad 5 ad 2 1 ad 7 ad 2 5 ad 6 ad 2 2 ad 8 ad 9 reser ved ad 2 3 ad 2 4 bfc l ki ad 2 8 ad 2 9 a1 4 cke v ddp a2 3 a2 2 v ddp v ss v ss a2 1 v ss tck p0 . 5 p2 . 0 p2 . 6 p0 . 0 trst p0 . 4 p4 . 3 hw cfg2 p4 . 6 p4 . 4 tdo p0 . 5 p0 . 2 p0 . 7 p0 . 1 1 tms p4 . 1 p0 . 1 2 p0 . 1 4 trclk p4 . 0 p0 . 1 3 p4 . 2 nmi p4 . 5 p0 . 1 5 hdrst p4 . 7 po r st br ki n ad 1 1 ad 1 2 ad 1 5 ad 3 0 a1 0 a1 1 a1 2 a1 3 cs comb mr /w al e rd/wr ad 2 6 ad 2 7 ad 3 1 ad1 4 a5 a6 a7 a8 a9 rd mii_ rxclk mii_ txc lk a3 mii_ md io a4 a2 a1 a0 sdcl ki sdcl ko ad 1 3 ad 1 0 bfc l ko 208-pin p-lbga package pin configuration (top view) for tc1130 v ss
tc1130 data sheet 6 v0.3, 2003-09 table 1 pin definitions and functions symbol pin in out pu/ pd 1) functions p0 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.11 n11 p15 p19 m15 r11 r12 r10 n10 r13 r15 r14 n9 i/o i/o i/o i/o o i/o i/o i/o o i/o i o i/o i i o i/o i/o i o i/o o i i o o i i i i o o i o puc puc puc puc puc puc puc puc puc puc puc puc port 0 port 0 is a 16-bit bidirectio nal general purpose i/o port which can be alternatively used for gptu, multican, asc1/2, ssc0/1, mli0, ebu and scu. gptu_0 gptu input/output line 0 rxd1b asc1 receiver input/output b gptu_1 gptu input/output line 1 txd1b asc1 transmitter output b gptu_2 gptu input/output line 2 rxd2b asc2 receiver input/output b gptu_3 gptu input/output line 3 txd2b asc2 transmitter output b gptu_4 gptu input/output line 4 slsi1 ssc1 slave select input breq ebu bus request output gptu_5 gptu input/output line 5 hold ebu hold request input cc60_t12hr ccu0 timer 12 hardware run brkout#_b ocds break out b gptu_6 gptu input/output line 6 hlda ebu hold acknow ledge input/output cc60_t13hr ccu0 timer 13 hardware run slso0_0 ssc0 slave select output 0 gptu_7 gptu input/output line 7 slso1_0 ssc1 slave select output 0 rxdcan0_a can node 0 receiver input a req0 external trigger input 0 tclk0a mli0 transmit ch annel clock output a txdcan0_a can node 0 transmitter output a tready0a mli0 transmit channel ready input a req1 external trigger input 1 rxdcan1_a can node 1 receiver input a req2 external trigger input 2 tvalid0a mli0 transmit channel valid output a txdcan1_a can node 1 transmitter output a req3 external trigger input 3 tdata0a mli0 transmit ch annel data output a
tc1130 data sheet 7 v0.3, 2003-09 p0.12 p0.13 p0.14 p0.15 p9 p8 n8 p7 i i i o i o i i i o i i puc puc puc puc rxdcan2 can node 2 receiver input rclk0a mli0 receive channel clock input a req4 external trigger input 4 txdcan2 can node 2 transmitter output req5 external trigger input 5 rready0a mli0 receive channel ready output a rxdcan3 can node 3 receiver input req6 external trigger input 6 rvalid0a mli0 receive channel valid input a txdcan3 can node 3 transmitter output req7 external trigger input 7 rdata0a mli0 re ceive channel data input a table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 8 v0.3, 2003-09 p1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 d11 c12 d12 b12 c11 c13 a12 i/o o i i o o i o o o i i o o o i o o i o o i o o i o puc puc puc puc puc puc puc port 1 port 1 serves as 16-bit bidi rectional general purpose i/ o port which can be used for input/output for ethernet controller, multican, can, ocds l2, ssc0/1, ebu and scu mii_txd0 ethernet cont roller transmit data output line 0 rxdcan0_b can node 0 receiver input b swcfg0 software configuration 0 ocdsa_0 ocds l2 debug line a0 mii_txd1 ethernet cont roller transmit data output line 1 swcfg1 software configuration 1 txdcan0_b can node 0 transmitter output b ocdsa_1 ocds l2 debug line a1 mii_txd2 ethernet cont roller transmit data output line 2 rxdcan1_b can node 1 receiver input b swcfg2 software configuration 2 ocdsa_2 ocds l2 debug line a2 mii_txd3 ethernet cont roller transmit data output line 3 txdcan1_b can node 1 transmitter output b swcfg3 software configuration 3 ocdsa_3 ocds l2 debug line a3 mii_txer ethernet contro ller transmit error output line swcfg4 software configuration 4 ocdsa_4 ocds l2 debug line a4 mii_txen ethernet controller transmit enable output line swcfg5 software configuration 5 ocdsa_5 ocds l2 debug line a5 mii_mdc ethernet contro ller management data clock output line swcfg6 software configuration 6 ocdsa_6 ocds l2 debug line a6 table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 9 v0.3, 2003-09 p1.7 p1.8 p1.9 p1.10 p1.11 p1.12 p1.13 p1.14 p1.15 b13 a13 a14 b14 c14 f13 e14 d14 f14 i i o i i o i i o i i o i i o o i i o o o i o o i o i o i o i o puc puc puc puc puc puc puc puc puc mii_rxdv ethernet contro ller receive data valid input line swcfg7 software configuration 7 ocdsa_7 ocds l2 debug line a7 mii_crs ethernet controll er carrier input line swcfg8 software configuration 8 ocdsa_8 ocds l2 debug line a8 mii_col ethernet controller collision input line swcfg9 software configuration 9 ocdsa_9 ocds l2 debug line a9 mii_rxd0 ethernet contro ller receive data input line 0 swcfg10 software configuration 10 ocdsa_10 ocds l2 debug line a10 mii_rxd1 ethernet contro ller receive data input line 1 swcfg11 software configuration 11 ocdsa_11 ocds l2 debug line a1 slso0_1 ssc0 slave select output 1 mii_rxd2 ethernet contro ller receive data input line 2 swcfg12 software configuration 12 ocdsa_12 ocds l2 debug line a12 slso1_1 ssc1 slave select output 1 mii_rxd3 ethernet contro ller receive data input line 3 swcfg13 software configuration 13 ocdsa_13 ocds l2 debug line a13 slso0_2 ssc0 slave select output 2 mii_rxer ethernet controll er receive error input line slso1_2 ssc1 slave select output 2 swcfg14 software configuration 14 ocdsa_14 ocds l2 debug line a14 slsi0 ssc0 slave select input rmw ebu read modify write swcfg15 software configuration 15 ocdsa_15 ocds l2 debug line a15 table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 10 v0.3, 2003-09 p2 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p2.8 p2.9 p2.10 p2.11 p2.12 p12 p11 p13 p14 n15 n14 n12 k16 j16 h16 l13 g16 k15 i/o i/o o o i i/o i/o i/o o i/o i/o i/o o i/o i/o i/o o o i/o i/o o o i/o i o puc puc puc puc puc puc puc puc puc puc puc puc ? port 2 port 2 is a 16-bit bidirectio nal general purpose i/o port which can be alternatively used for asc0/1/2, ssc0/1, ccu0, iic, ebu and scu. rxd0 asc0 receiver input/output line csemu ebu chip select output for emulator region txd0 asc0 transmitter output line testmode test mode select input mrst0 ssc0 master receive / slave transmit input/output mtsr0 ssc0 master tran smit / slave receive input/output sclk0 ssc0 clock input/output line cout60_3 ccu0 compar e channel 3 output mrst1a ssc1 master receive / slave transmit input/output a cc60_0 ccu0 inpu t/output of capture/compare channel 0 mtsr1a ssc1 master tran smit / slave receive input/output a cout60_0 ccu0 output of capture/compare channel 0 sclk1a ssc1 clock input/output line a cc60_1 ccu0 input/output of capture/ compare channel 1 rxd1a asc1 receiver input/output line a cout60_1 ccu0 output of capture/compare channel 1 txd1a asc1 transmitter output line a cc60_2 ccu0 input/output of capture/ compare channel 2 rxd2a asc2 receiver input/output line a cout60_2 ccu0 output of capture/compare channel 2 txd2a asc2 transmitter output line a sda0 iic serial data line 0 ctrap0 ccu0 trap input slso0_3 ssc0 slave select output 3 table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 11 v0.3, 2003-09 p2.13 p2.14 p2.15 k14 f16 e16 i/o i o i i/o o i i/o o ? ? ? scl0 iic clock line 0 ccpos0_0 ccu0 hall input signal 0 slso1_3 ssc1 slave select output 3 ccpos0_1 ccu0 hall input signal 1 sda1 iic serial data line 1 slso0_4 ssc0 slave select output 4 ccpos0_2 ccu0 hall input signal 2 scl1 iic clock line 1 slso1_4 ssc1 slave select output 4 table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 12 v0.3, 2003-09 p3 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 a15 b15 d15 e15 g14 g15 f15 h14 c15 h15 b16 i/o o o o i/o o o o i/o o o o i/o o o o i o o i o o o i i o o i o o puc puc puc puc puc puc puc puc puc puc puc port 3 port 3 is a 16-bit bidirectio nal general purpose i/o port which can be alternativel y used for mli1, ccu1, ssc0/1 and ocds level 2 debug lines. ocdsb_0 ocds l2 debug line b0 cout61_3 ccu1 compare channel 3 output ocdsb_1 ocds l2 debug line b1 cc61_0 ccu1 input/output of capture/ compare channel 0 ocdsb_2 ocds l2 debug line b2 cout61_0 ccu1 output of capture/compare channel 0 ocdsb_3 ocds l2 debug line b3 cc61_1 ccu1 input/output of capture/ compare channel 1 ocdsb_4 ocds l2 debug line b4 cout61_1 ccu1 output of capture/compare channel 1 ocdsb_5 ocds l2 debug line b5 cc61_2 ccu1 input/output of capture/ compare channel 2 ocdsb_6 ocds l2 debug line b6 cout61_2 ccu1 output of capture/compare channel 2 ocdsb_7 ocds l2 debug line b7 ctrap1 ccu1 trap input slso0_5 ssc0 slave select output 5 ocdsb_8 ocds l2 debug line b8 ccpos1_0 ccu1 hall input signal 0 tclk1 mli1 transmit channel clock output slso1_5 ssc1 slave select output 5 ocdsb_9 ocds l2 debug line b9 ccpos1_1 ccu1 hall input signal 1 tready1 mli1 transmit channel ready input slso0_6 ssc0 slave select output 6 ocdsb_10 ocds l2 debug line b10 ccpos1_2 ccu1 hall input signal 2 tvalid1 mli1 transmit channel valid output slso1_6 ssc1 slave select output 6 table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 13 v0.3, 2003-09 p3.11 p3.12 p3.13 p3.14 p3.15 c16 d16 k13 j14 j15 o o o i o i o i o o i/o o i i/o o i i/o puc puc puc puc puc ocdsb_11 ocds l2 debug line b11 tdata1 mli1 transmit channel data output slso0_7 ssc0 slave select output 7 cc61_t12hr ccu1 timer 12 hardware run ocdsb_12 ocds l2 debug line b12 rclk1 mli1 receive channel clock input slso1_7 ssc1 slave select output 7 cc61_t13hr ccu1 timer 13 hardware run ocdsb_13 ocds l2 debug line b13 rready1 mli1 receive channel ready output mrst1b ssc1 master receive / slave transmit input/output b ocdsb_14 ocds l2 debug line b14 rvalid1 mli1 receive channel valid input mtsr1b ssc1 master transmit / slave receive input/output b ocdsb_15 ocds l2 debug line b15 rdata1 mli1 receive channel data input sclk1b ssc1 clock input/output line b table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 14 v0.3, 2003-09 p4 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 r8 r9 n7 n6 p6 r7 r6 p5 i/o i o i i i o i o o i o o o i i o puc puc puc puc puc puc puc puc port 4 port 4 is a 8-bit bidirecti onal general purpose i/o port which can be alternatively used for usb, mli0 and scu. usbclk 48mhz input clock tclk0b mli0 transmit ch annel clock output b rcvi usb data input tready0b mli0 transmit channel ready input b vpi u sb d+ cmos level mirror of differential signal tvalid0b mli0 transmit channel valid output b vmi usb d- cmos le vel mirror of differential signal tdata0b mli0 transmit ch annel data output b vpo usb d+ cmos level output rclk0b mli0 receive channel clock input b vmo usb d- cmos level output rready0b mli0 receive ch annel ready output b usboe direction select fo r transmit or receive rvalid0b mli0 receive channel valid input b rdata0b mli0 receive ch annel data input b brkout#_a ocds break out a hdrst n5 i/o pua hardware reset input/reset indication output assertion of this bidirectio nal open-drain pin causes a synchronous reset of the chip through external circuitry. this pin must be driven for a minimum duration. the internal reset circuitry dr ives this pin in response to a power-on, hardware , watchdog and power-down wake-up reset for a specific period of time. for a software reset, activation of this pin is programmable. porst r5 i puc power-on reset input a low level on porst causes an asynchronous reset of the entire chip. porst is a fully asynchronous level sensitive signal. nmi t7 i puc non-maskable interrupt input a high-to-low transition on th is pin causes a nmi-trap request to the cpu. table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 15 v0.3, 2003-09 trst t11 i pdc jtag module reset/enable input a low level at this pin rese ts and disables the jtag module. a high level e nables the jtag module. tck t12 i puc jtag module clock input tdi t13 i puc jtag module serial data input tdo t10 o ? jtag module serial data output tms t9 i puc jtag module state machine control input trclk t8 o ? trace clock for ocds_l2 lines hwcfg0 hwcfg1 hwcfg2 m14 l14 t6 i i i puc puc pdc hardware confi guration inputs the configuration inputs defi ne the boot op tions of the tc1130 after a hardware invoked reset operation. brkin t5 i puc ocds break input a low level on this pin caus es a break in the chip?s execution when the ocds is enabled. in addition, the level of this pin during power-on reset determines the boot configuration. mii_ txclk t2 i pdc ethernet controller transmit clock mii_txd[3:0] and mii_txen are driven off the rising edge of the mii_txclk by the core and sampled by the phy on the rising edge of the mii_txclk. mii_ rxclk r2 i pdc ethernet controller receive clock mii_rxclk is a continuous clock. its frequency is 25 mhz for 100 mbps operation, and 2. 5 mhz for 10mbps. mii_rxd[3:0], mii_rxdv and mii_exer are driven by the phy off the falling edge of mii_rxclk and sampled on the rising edge of mii_rxclk. mii_ mdio r1 i/o pda ethernet controller ma nagement data input / output when a read command is be ing executed, data which is clocked out of t he phy will be pres ented on the input line. when the core is clocki ng control or data onto the mii_mdio line, the signal wi ll carry the information. d+ t14 i/o ? usb d+ data line d- t15 i/o ? usb d- data line table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 16 v0.3, 2003-09 cs0 cs1 cs2 cs3 d9 d8 c9 b8 o o o o puc puc puc puc ebu chip select output line 0 ebu chip select output line 1 ebu chip select output line 2 ebu chip select output line 3 each corresponds to a pr ogrammable region. only one can be active at one time. cscomb n3 o puc ebu chip select output for combination function (overlay memory and global) sdclki j1 i ? sdram clock input (clock feedback). sdclko h1 o ? sdram clock output.accesse s to sdram devices are synchronized to this clock ras d6 o puc ebu sdram row address strobe output cas d5 o puc ebu sdram column address strobe output cke l4 o puc ebu sdram clock enable output bfclki d1 i ? burst flash clock in put (clock feedback). bfclko e1 o ? burst flash clock output. accesses to burst flash devices are synchronized to this clock. rd p2 o puc ebu read control line output in the master mode input in the slave mode. rd/wr t3 o puc ebu write control line output in the master mode input in the slave mode. wait b9 i puc ebu wait control line ale r3 o pdc ebu address latch enable output mr/w p3 o puc ebu motorola-style read / write output baa a11 o puc ebu burst address advance output for advancing address in a burst flash access adv b11 o puc ebu burst flash a ddress valid output table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 17 v0.3, 2003-09 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 c8 c7 b6 c6 c5 a3 a2 c3 c2 d2 f1 e3 f3 g1 h2 g3 d7 b5 a4 b4 c4 b3 b2 b1 c1 d3 e2 f2 f4 g4 h3 g2 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc ebu address / data bus input / output lines ebu address / data bus line 0 ebu address / data bus line 1 ebu address / data bus line 2 ebu address / data bus line 3 ebu address / data bus line 4 ebu address / data bus line 5 ebu address / data bus line 6 ebu address / data bus line 7 ebu address / data bus line 8 ebu address / data bus line 9 ebu address / data bus line 10 ebu address / data bus line 11 ebu address / data bus line 12 ebu address / data bus line 13 ebu address / data bus line 14 ebu address / data bus line 15 ebu address / data bus line 16 ebu address / data bus line 17 ebu address / data bus line 18 ebu address / data bus line 19 ebu address / data bus line 20 ebu address / data bus line 21 ebu address / data bus line 22 ebu address / data bus line 23 ebu address / data bus line 24 ebu address / data bus line 25 ebu address / data bus line 26 ebu address / data bus line 27 ebu address / data bus line 28 ebu address / data bus line 29 ebu address / data bus line 30 ebu address / data bus line 31 bc0 bc1 bc2 bc3 a5 a6 b7 a7 o o o o puc puc puc puc ebu byte control line 0 ebu byte control line 1 ebu byte control line 2 ebu byte control line 3 table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 18 v0.3, 2003-09 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 k1 l1 m1 n1 p1 j2 k2 l2 m2 n2 j3 k3 l3 m3 k4 a8 a9 a10 b10 c10 d10 t4 r4 p4 o o o o o o o o o o o o o o o o o o o o o o o o puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc ebu address bus input / output lines ebu address bus line 0 ebu address bus line 1 ebu address bus line 2 ebu address bus line 3 ebu address bus line 4 ebu address bus line 5 ebu address bus line 6 ebu address bus line 7 ebu address bus line 8 ebu address bus line 9 ebu address bus line 10 ebu address bus line 11 ebu address bus line 12 ebu address bus line 13 ebu address bus line 14 ebu address bus line 15 ebu address bus line 16 ebu address bus line 17 ebu address bus line 18 ebu address bus line 19 ebu address bus line 20 ebu address bus line 21 ebu address bus line 22 ebu address bus line 23 xtal1 xtal2 m16 n16 i o ? ? oscillator/pll/clock gene rator input/output pins xtal1 is the input to the main oscill ator amplifier and input to the internal clo ck generator. xtal2 is the output of the main oscillat or amplifier circuit. for clocking the device from an external sour ce, xtal1 is driven with the clock sign al while xtal2 is left unconnected. for crystal oscillator operation xtal1 and xtal2 are connected to the crystal with the appropriate recommended oscillator circuitry. v ddosc3 p16 ?? main oscillator power supply (3.3v) v ssosc3 r16 ?? main oscillator ground v ddosc l16 ?? main oscillator power supply (1.5v) table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 19 v0.3, 2003-09 v ssosc l15 ?? main oscillator ground v dd g7, g8 g9 g10 g13 k7,k8 k9 k10 ?? core and logic power supply (1.5v) v ddp d4, d13, h4, j13, m4, n13, ?? ports power supply (3.3v) v ss e4 e13 h7, h8 h9 h10 h13 j4,j7 j8,j9 j10 m13 n4 ?? ground n.c. a1, a16, t1, t16 ?? not connected these pins must not be connected. 1) refers to internal pull-up or pull-down devi ce connected and corresponding type. the notation ? ? ? indicates that the internal pull-up or pull-down device is not enabled. table 1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
tc1130 data sheet 20 v0.3, 2003-09 parallel ports the tc1130 has 72 digita l input/output port lines, which are organized into four parallel 16-bit ports and one parallel 8-bit port, port p0 to port p4 with 3.3v nominal voltage. the digital parallel ports can be all used as general purpos e i/o lines or they can perform input/output functions for th e on-chip peripheral units. an overview on the port-to- peripheral unit assign ment is shown in figure 4 . figure 4 parallel ports of the tc1130 mca04951mod tc1130 paral l el ports gpio3 gpio4 gpio alternate functions ssc0/ ssc1/ ccu61/ mli1/ ocds usb/ mli0/ scu gpio1 gpio0 gpio2 gpio alternate functions asc0/ asc1/ asc2/ ssc0/ ssc1/ iic/ ccu60/ebu/ scu ssc0/ ssc1/ mul ti can/ ethernet/ ebu/ scu/ ocds gptu/ asc1/ asc2/ ssc0/ ssc1/ ccu60/ multican/ mli0/ ebu/ scu/ external interrupts 16 16 16 8 16
tc1130 data sheet 21 v0.3, 2003-09 serial interfaces the tc1130 includes five seri al peripheral interface units: ? asynchronous/synchronous serial interface (asc) ? high-speed synchronous serial interface (ssc) ? inter ic serial interface (iic) ? universal serial bus interface (usb) ? micro link serial bus interface (mli) asynchronous/synchronous serial interface (asc) figure 5 shows a global view of the functional block of three asynchronous/ synchronous serial interfac es (asc0, asc1 and asc2). each asc module, (asc0/asc1/ asc2) communicates with th e external world via one pair of i/o lines. the rxd lin e is the receive data input sign al (in synchronous mode also output). txd is the transmit ou tput signal. clock control, address decoding, and interrupt service request control are manage d outside the asc module kernel. the asynchronous/synchronous serial in terfaces provide serial communication between the tc1130 and ot her microcontrollers, microprocessors or external peripherals. each asc supports full-duplex asynch ronous communication and half-duplex synchronous communicati on. in synchronous mode, data is transmitted or received synchronous to a shift clock which is generated by the asc internally. in asynchronous mode, 8-bit or 9-bit data tran sfer, parity generation, and the number of stop bits can be selected. parity, framing, an d overrun error detection ar e provided to increase the reliability of data transfers. transmission and reception of data are double-buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. testing is supported by a loop-back option. a 13-b it baud rate generator provides the asc with a separate serial clock signal that ca n be very accurately adjusted by a prescaler implemented as a fractional divider.
tc1130 data sheet 22 v0.3, 2003-09 figure 5 general block diag ram of the asc interfaces mcb04485_mod asc0 module (kernel) port control asc1 module (kernel) clock control address decoder interrupt control f asc1 to dma eir tbir tir rir clock control address decoder interrupt control f asc0 to dma eir tbir tir rir p2.0/ rxd0 p2.1/ txd0 p0.0/ rxd1b p0.1/ txd1b p2.8/ rxd1a p2.9/ txd1a rxd_i1 rxd_o rxd_i0 txd_o rxd_i1 rxd_o rxd_i0 txd_o asc2 module (kernel) clock control address decoder interrupt control f asc1 to dma eir tbir tir rir p0.2/ rxd2b p0.3/ txd2b p2.10/ rxd2a p2.11/ txd2a rxd_i1 rxd_o rxd_i0 txd_o
tc1130 data sheet 23 v0.3, 2003-09 features: full-duplex asynchro nous operating modes ? 8-bit or 9-bit data frames, lsb first ? parity bit generation/checking ? one or two stop bits ? baud rate from 4. 6875 mbaud to 1.1 baud (@ 75 mhz clock) multiprocessor mode for automati c address/data byte detection loop-back capability half-duplex 8-bit sync hronous operating mode ? baud rate from 9. 375 mbaud to 762.9 baud (@ 75 mhz clock) support for irda data transmi ssion up to 115. 2 kbaud maximum. double buffered transmitter/receiver interrupt generation ? on a transmitter buffer empty condition ? on a transmit last bit of a frame condition ? on a receiver buffer full condition ? on an error condition (fra me, parity, overrun error) fifo ? 8 byte receive fifo (rxfifo) ? 8 byte transmit fifo (txfifo) ? independent control of rxfifo and txfifo ? 9-bit fifo data width ? programmable receive/transm it interrupt trigger level ? receive and transmit fifo filling level indication ? overrun error generation ? underflow error generation
tc1130 data sheet 24 v0.3, 2003-09 high-speed synchronous se rial interface (ssc) figure 6 shows a global view of th e functional blocks of tw o high-speed synchronous serial interfaces (ssc0 and ssc1). each ssc supports full-duple x and half-duplex serial synch ronous communication up to 37.5 mbaud (@ 75 mhz module clock) with receive and transmit fifo support. the serial clock signal can be generated by the ssc itself (master mode ) or can be received from an external master (sla ve mode). data widt h, shift direction, clock polarity and phase are programmable. this allows co mmunication with spi-compatible devices. transmission and reception of data is double-bu ffered. a shift clo ck generator provides the ssc with a separate serial clock signal. eight slave se lect inputs are available for slave mode operation. eight programmable slave select outputs (chip selects) are supported in master mode. features: master and slave mode operation ? full-duplex or ha lf-duplex operation ? automatic pad control possible flexible data format ? programmable number of data bits: 2 to 16 bit ? programmable shift directio n: lsb or msb shift first ? programmable clock polarity: idle lo w or high state fo r the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock baud rate generation minimum at 572.2 baud (@ 75 mhz module clock) interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, baud rate, transmit error) four-pin interface flexible ssc pin configuration up to eight slave select inputs in slave mode up to eight programmable slave sele ct outputs slso in master mode ? automatic slso generation with programmable timing ? programmable active le vel and enable control 4-stage receive fifo (rxfifo) a nd 4-stage transmit fifo (txfifo) ? independent control of rxfifo and txfifo ? 2 to 16 bit fifo data width ? programmable receive/transm it interrupt trigger level ? receive and transmit fifo filling level indication ? overrun error generation ? underflow error generation
tc1130 data sheet 25 v0.3, 2003-09 figure 6 general block diag ram of the ssc interfaces port 1 control mcb04486_mod clock control address decoder interrupt control f ssc0 address decoder interrupt control to dma eir tir rir to dma eir tir rir port 2 control ssc0 module (kernel) mrstb mtsr master slsi1 slso[2:1] mrsta mtsrb mrst mtsra sclkb slck sclka slave slave master slave master port 2 control ssc1 module (kernel) mrstb mtsr master slso[7:5] mrsta mtsrb mrst mtsra sclkb slck sclka slave slave master master p2.3/mtsr0 p2.2/mrst0 p2.4/sclk0 p2.5/mrst1a p1.15/slsi0 f clc0 f ssc1 f clc1 clock control slsi[7:2] 1) slsi1 slave slsi[7:2] 1) enable m/s select p1.11/slso01 1) these lines are not connected slso0 enable 1) m/s select 1) 1) 1) p1.13/slso02 p2.12/slso03 p2.14/slso04 slso[4:3] port 0 control p0.6/slso00 p0.7/slso10 port 3 control slso[7:5] p3.7/slso05 p3.9/slso06 p3.11/slso07 p3.8/slso15 p3.10/slso16 p3.11/slso17 slso0 slso[2:1] slso[4:3] port 1 control p1.12/slso11 p1.14/slso12 p3.13/mrst1b p2.6/mtsr1a p3.14/mtsr1b p2.7sclk1a p3.15/sclk1b p2.13/slso13 p2.15/slso14 p0.4/slsi1
tc1130 data sheet 26 v0.3, 2003-09 inter ic serial interface (iic) figure 7 shows a global view of the functional blocks of the inte r ic serial in terface (iic). the iic module has four i/o lines, located at port 2. the iic module is further supplied by a clock control, interrupt control, and address decoding logic. one dm a request can be generated by iic module. figure 7 general block diag ram of the iic interface the on-chip iic bus module co nnects the platform buses to other external controllers and/or peripherals via the two-li ne serial iic interface. one line is responsible for clock transfer and synchronization (scl), the other is responsible for the data transfer (sda). the iic bus module provides communication at data rates of up to 400 kbit/s and features 7-bit addressing as well as 10-bit addressing. this module is fully compatible to the iic bus protocol. the module can operate in three different modes: master mode , where the iic controls the bus transa ctions and provides the clock signal. slave mode , where an external master controls the bus transactions and provides the clock signal. multimaster mode , where several masters can be connect ed to the bus, i.e. the iic can be master or slave. the on-chip iic bus module allows efficien t communication via th e common iic bus. the module unloads the cpu of low level tasks like (de)serialization of bus data. generation of start and stop co nditions. monitoring the bus lines in slave mode. evaluation of the device address in slave mode. bus access arbitration in multimaster mode. address decoder interrupt control iic module port 2 control p2.13/scl0 p2.15/scl1 sda0 p2.14/sda1 p2.12/sda0 clock control f iic scl0 sda1 scl1 int_p int_e int_d to dma
tc1130 data sheet 27 v0.3, 2003-09 features software compatible to v1.0 of c161ri. extended buffer allows up to 4 send /receive data byte s to be stored. selectable baud rate generation. support of standard 100 kbaud and extended 400 kbaud data rates. operation in 7-bit addressing m ode or 10-bit addressing mode. flexible control via interrupt se rvice routines or by polling. dynamic access to up to 2 physical iic busses.
tc1130 data sheet 28 v0.3, 2003-09 universal serial bus interface (usb) figure 8 shows a global view of the functional blocks of the universal serial bus interface (usb). the usb module is further supplied by clock control, interrupt co ntrol, address decoding, and port control logic. one dma request can be gen erated by usb module. figure 8 general block diagram of the usb the usb handles all transaction s between the serial usb bus and the internal (parallel) bus of the microcontroller. th e usb module includes several units which are required to support data handling with the usb bus: the on-chip usb transceiver (optionally), the flexible usb buffer block with a 32 bit wide ram, the buffer control unit with sub modules for usb and cpu memory access control, the udc_if device interface for usb protocol handling, the microcontroller interface unit (mcu) with the usb specific special function registers and the interrupt generation unit. a clock generation unit provides the clock signal for the usb module for full speed and lo w speed usb operation. interrupt control usb modul e (kernel) cl oc k control address decoder f usb to dma isr0 isr1 port 4 control p4.4 /vpo p4.0 /usbclk vpob vmob vmib usboeb usbclkb rcvib vpib p4.1 /rcvi p4.2 /vpi p4.3 /vmi p4.5 /vmo p4.6 /usboe isr2 isr3 isr4 isr5 isr6 isr7 d+ d-
tc1130 data sheet 29 v0.3, 2003-09 features usb1.1 device st andard interface differential i/o allow cable length up to 5m without additional hardware at target?s end. hot attach usb1.1 full speed device usb protocol handling in hardware clock and data recovery from usb bit stripping and bi t stuffing functions crc5 checking, crc16 g eneration and checking serial to parall el data conversion maintenance of data synchronization bits (data0/data1 toggle bits) supports multiple configurations, interfaces and alternate settings sixteen endpoints with user c onfigurable endpoint information flexible intermediate buffe ring of transmission data powerful data handling ca pability, fifo-support back-to-back transfers fully supported by mo dule automatism multi packet transfer without cpu load handles data transfer with minimum cpu load auto increment and single address mo des selectable fo r easy data access powerful interrupt generation meets suspend power consumption restrictions in power down mode remote wakeup from usb bus activity explicit support of setup information enhanced status monitoring
tc1130 data sheet 30 v0.3, 2003-09 micro link serial bus interface (mli) figure 9 shows a global view of the functional blocks of two micro link serial bus interfaces (mli0 & mli1). figure 9 general block diag ram of the mli0 and mli1 interrupt control mli_inter fac es cl ock control address decoder f ml i0 mli interface mli0 module (kernel) treadya port 0 control tvalida tdata tclk rreadya rvalida rdataa rclka p0.8/ tclk0a p0.9/ tready0a p0.10/ tvalid0a p0.11/ tdata0a p0.12/rclk0a p0.13/ rready0a p0.14/ rvalid0a p0.15/ rdata0a dma int_o [3:0] int_o [7:4] treadyb port 4 control tvalidb tdata tclk rreadyb rvalidb rdatab rclkb p4.0/ tclk0b p4.1/ tready0b p4.2/ tvalid0b p4.3/ tdata0b p4.4/rclk0b p4.5/ rready0b p4.6/ rvalid0b p4.7/ rdata0b interrupt control cl ock control address decoder f ml i1 mli interface mli1 module (kernel) treadya port 3 control tvalida tdata tclk rreadya rvalida rdataa rclka p3.8 /tclk1 p3.9 / tready1a p3.10 / tvalid1a p3.11 / tdata1 p3.12/ rclk1a p3.13 / rready1a p3.14 / rvalid1a p3.15 / rdata1a dma int_o [1:0] int_o [7:4]
tc1130 data sheet 31 v0.3, 2003-09 the micro link serial bus interface is dedi cated for the serial communication between controllers of the audo - ng family. the communication is intended to be fast and intelligent due to an address translation syste m, and it is not necessary to have any special program in the second controller. features: serial communication from th e mli transmitter to mli rece iver of another controller module supports connection of each mli with up to four mli from other controllers (see implementation sub-chapter for details for this product) fully transparent read /write access supported (= remote programming) complete address range of ta rget controller available special protocol to transfer data, ad dress offset, or addr ess offset and data error control using a parity bit 32 - bits, 16 - bits, and 8 - bits data transfers address offset width: from 1 to 16 - bits baud rate: f mli / 2 (symmetric shift clock approach), baud rate definition by the corresponding fractional divider
tc1130 data sheet 32 v0.3, 2003-09 general purpose timer unit figure 10 shows a global view of all functional blocks of the general purpose timer unit (gptu). figure 10 general block diagra m of the gptu interface the gptu consists of three 32-bit timers designed to solve su ch application tasks as event timing, event counting , and event recording. the gptu communicates with the external world via eight i/ o lines located at port 0. the three timers of gptu module t0, t1, and t2, can operate in dependently from each other or can be combined: general features: all timers are 32-bit precision time rs with a maximum input frequency of f gptu . events generated in t0 or t1 can be used to trigger actions in t2 timer overflow or underfl ow in t2 can be used to clock either t0 or t1 t0 and t1 can be concatenat ed to form one 64-bit timer features of t0 and t1: each timer has a dedicated 32 -bit reload register with automatic relo ad on overflow timers can be split into indi vidual 8-, 16-, or 24-bit ti mers with individual reload registers clock control address decoder interrupt control f gptu0 gptu module port 0 control p0.0/gptu_0 sr0 sr1 sr2 sr3 sr4 sr5 sr6 sr7 in0 in1 in2 in3 in4 in5 in6 in7 out0 out1 out2 out3 out4 out5 out6 out7 p0.1/gptu_1 p0.2/gptu_2 p0.3/gptu_3 p0.4/gptu_4 p0.5/gptu_5 p0.6/gptu_6 p0.7/gptu_7
tc1130 data sheet 33 v0.3, 2003-09 overflow signals can be selected to generate service requests, pin output signals, and t2 trigger events two input pins can define a count option features of t2: count up or down is selectable operating modes: ?timer ? counter ? quadrature counter (incremental/p hase encoded counter interface) options: ? external start/stop, on e-shot operation, timer clear on external event ? count direction control through software or an external event ? two 32-bit reload/capture registers reload modes: ? reload on overflow or underflow ? reload on external event: positive transit ion, negative transiti on, or both transitions capture modes: ? capture on external event: positive transition, nega tive transition, or both transitions ? capture and clear timer on external event: positive transition, negative transition, or both transitions can be split into tw o 16-bit counter/timers timer count, reload, capture, and trigger functions can be assigned to input pins. t0 and t1 overflow events can also be assign ed to these functions. overflow and underflow signal s can be used to trigger t0 and/or t1 and to toggle output pins t2 events are freely assignabl e to the servic e request nodes.
tc1130 data sheet 34 v0.3, 2003-09 capture/compare unit 6 (ccu6) figure 11 shows a global view of all functional blocks of two capture/compare units (ccu60 & ccu61). both of the ccu6 modules is further supplied by cl ock control, interrupt control, address decoding, and port control logic. one dma request can be ge nerated by each ccu6 module. each ccu6 provides two independent ti mers (t12, t13), which can be used for pwm generation, especially for ac-mo tor control. additionally, sp ecial control modes for block commutation and multi-phas e machines are supported. timer 12 features three capture/compare channel s, each channel can be used either as capture or as compare channel. generation of a three-phase pwm supporte d (six outputs, indi vidual signals for highside and lowside switches) 16 bit resolution, maximum coun t frequency = peripheral clock dead-time control for each channel to avoid short-ci rcuits in the power stage concurrent update of t he required t12/13 registers center-aligned and edge-ali gned pwm can be generated single-shot m ode supported many interrupt request sources hysteresis-like control mode timer 13 features one independent compare ch annel with one output 16 bit resolution, maximum coun t frequency = peripheral clock can be synchronized to t12 interrupt generation at per iod-match and compare-match single-shot m ode supported additional features block commutation for brushl ess dc-drives implemented position detection vi a hall-sensor pattern automatic rotational speed meas urement for block commutation integrated error handling fast emergency stop without cpu lo ad via external signal (ctrap ) control modes for mu lti-channel ac-drives output levels can be selected and adapted to the power stage
tc1130 data sheet 35 v0.3, 2003-09 figure 11 general block diagram of the ccu6 interrupt control tc1130_ccu6_imple ccu60 module (kernel) port 2 control to dma clock control address decoder f ccu to dma src0 src1 src2 src3 p2.6 /cc600 p2.12 /ctrap0 cc62 cout62 cout61 cout63 cc60 cout60 ccpos2 cc61 /ctrap ccpos0 ccpos1 p2.13 /ccpos00 p2.14 /ccpos01 p2.15 /ccpos02 p2.7 /cout600 p2.8 /cc601 p2.9 /cout601 p2.10 /cc602 p2.11 /cout602 p2.5 /cout603 ccu61 module (kernel) port 3 control p3.1 /cc610 p3.7 /ctrap1 cc62 cout62 cout61 cout63 cc60 cout60 ccpos2 cc61 /ctrap ccpos0 ccpos1 p3.8 /ccpos10 p3.9 /ccpos11 p3.10 /ccpos12 p3.2 /cout610 p3.3 /cc611 p3.4 /cout611 p3.5 /cc612 p3.6 /cout612 p3.0 /cout613 src0 src1 src2 src3 p0.5 / ccu60_t12hr p0.6 / ccu60_t13hr t12hr t13hr p3.11 / ccu61_t12hr p3.12 / ccu61_t13hr t12hr t13hr
tc1130 data sheet 36 v0.3, 2003-09 multican figure 12 shows a global view of all functio nal blocks of the multican module. figure 12 general block diagra m of the multican interfaces the multican module contains 4 full-c an nodes operatin g independently or exchanging data and re mote frames via a gateway func tion. transmission and reception of can frames is handled in accordance to can specification v2.0 part b (active). each can node can receive and transm it standard frames with 11- bit identifiers as well as extended frames with 29-bit identifiers. all can nodes share a common set of message objects, where each message object may be individually allocate d to one of the can nodes. be sides serving as a storage container for incoming and outgoing frames, message objects may be combined to build gateways between the can nodes or to setup a fifo buffer. the message objects are organi zed in double chaine d lists, where each can node has it?s own list of message ob jects. a can node stores fram es only into message objects that are allocated to the list of the can node. it only transmits messages from objects of this list. a powerful, command driven list controller performs all list operations. multican module kernel multican_tc1130_impl interrupt control f can port 0 control can node 1 can control message object buffer 128 objects txdc0a rxdc0a can node 0 can node 2 can node 3 txdc1a rxdc1a txdc2 rxdc2 txdc3 rxdc3 linked list control p0.15 / txdcan3 p0.14 / rxdcan3 p0.13 / txdcan2 p0.12 / rxdcan2 p0.11 / txdcan1a p0.10 / rxdcan1a p0.9 / txdcan0a p0.8 / rxdcan0a f clc clock control address decoder dma int_o [3:0] int_o [15:4] int_o15 port 1 control p1.1 / txdcan0b p1.0 / rxdcan0b p1.3 / txdcan1b p1.2 / rxdcan1b txdc1b rxdc1b txdc0b rxdc0b
tc1130 data sheet 37 v0.3, 2003-09 the bit timings for the can nodes are derived from the peripheral clock (f can ) and are programmable up to a data rate of 1 mbaud. a pair of receive and transmit pins connects each can node to a bus transceiver. features compliant to iso 11898. can functionality according to can specification v2.0 b active. dedicated control registers ar e provided for each can node. a data transfer rate up to 1 mbaud is supported. flexible and powerful message transfer control and erro r handling capabilities are implemented. advanced can bus bit timing analysis and baud rate det ection can be performed for each can node via the frame counter. full-can functionality: a set of 128 message objects can be individually ? allocated (assigned) to any can node ? configured as transm it or receive object ? setup to handle frames with 11-bit or 29-bit identifier ? counted or assigned a time stamp via a frame counter ? configured to remo te monitoring mode advanced acceptance filtering: ? each message object provides an indivi dual acceptance mask to filter incoming frames. ? a message object can be configured to accept only standard or only extended frames or to accept both standard and extended frames. ? message objects can be grouped into 4 priority classes. ? the selection of the mess age to be transmitted first can be performed on the basis of frame identifier, ide bit and rtr bit according to can arbitration rules. advanced message ob ject functionality: ? message objects can be combined to buil d fifo message buffers of arbitrary size, which is only limited by the to tal number of message objects. ? message objects can be link ed to form a gateway to au tomatically transfer frames between 2 different can bus es. a single gatewa y can link any two can nodes. an arbitrary number of ga teways may be defined. advanced data management: ? the message objects are organi zed in double chained lists. ? list reorganizations may be performed any time, even during fu ll operation of the can nodes. ? a powerful, command driven list controller manages the organization of the list structure and ensures co nsistency of the list. ? message fifos are based on the list structure and ca n easily be scaled in size during can operation.
tc1130 data sheet 38 v0.3, 2003-09 ? static allocation commands offer compatib ility with twincan applications, which are not list based. advanced interru pt handling: ? up to 16 interrupt output lines are avai lable. most interru pt requests can be individually routed to one of the 16 inte rrupt output lines. ? message postprocessing noti fications can be flexibly aggregated into a dedicated register field of 2 56 notification bits.
tc1130 data sheet 39 v0.3, 2003-09 ethernet controller the mac controller implements the ieee 802.3 and operates either at 100 mbps or 10 mbps. figure 13 shows a global view of the ethernet controller module with the module specific interface connections. figure 13 general block diagram of the ethernet controller the ethernet controller comprise s the following functional blocks: 1. media access controller (mac) 2. receive buffer (rb) 3. transmit buffer (tb) 4. data management unit in receive direction (dmur) 5. data management unit in transmit direction (dmut) mcb04942mod port control p1.14 / mii_rxer fpi (m/s) p1.13 / mii_rxd[3] p1.12 / mii_rxd[2] p1.11 / mii_rxd[1] p1.10 / mii_rxd[0] p1.9 / mii_col p1.8 / mii_crs p1.7 / mii_rxdv p1.6 / mii_mdc p1.5 / mii_txen p1.4 / mii_txer p1.3 / mii_txd[3] p1.2 / mii_txd[2] p1.1 / mii_txd[1] p1.0 / mii_txd[0] mii_txclk mii_txclk mii_tdio mii mac ethernet controller rb tb dmur dmut
tc1130 data sheet 40 v0.3, 2003-09 rb as well as tb provid es on-chip data buffering whereas dmur and dmut perform data transfer from/to the shared memory. two interfaces are provided by the ethernet controller module: 1. mii interface for connectio n of ethernet phys via ei ghteen input / output lines 2. master/slave fpi bus interface for conn ection to the on-chi p system bus for data transfer as well as configuration. features media independent interface (mii) according to ieee 802.3 support 10 or 100 mbps mii-based physical devices. support full duplex ethernet. support data transfer between ethernet cont roller and com-dram. support data transfer between ethernet controll er and sdram via ebu. 256 x 32 bit receive buffer and transmit buffer each. support burst transfers up to 8 x 32 byte. media access controller (mac) 100/10-mbps operations full ieee 802.3 compliance station management signaling large on-chip cam (content addressable memory) full duplex mode 80-byte transmit fifo 16-byte receive fifo pause operation flexible mac control support support long packet mode and short packet mode pad generation media independent interface (mii) media independence. multi-vendor point of interoperability. support connection of mac layer and physical (phy) layer devices. capable of supportin g both 100 mb/s and 10 mb/s data rates. data and delimiters are synch ronous to clock references. provides independent four bit wide transmit and receive data paths. support connection of phy layer and station ma nagement (sta) devices. provides a simple management interface. capable of drivi ng a limited length of shielded cable.
tc1130 data sheet 41 v0.3, 2003-09 on-chip memories the tc1130 provides the fo llowing on-chip memories: program memory interface (pmi) with ? 32 kbytes scratch-pad code ram (sram) ? 16 kbytes instruction cache memory (i-cache) data memory interface (dmi) with ? 28 kbytes scratch-pad data ram (sram) ? 4 kbytes data cach e memory (d-cache) data memory unit (dmu) with ? 64 kbytes sram 16 kbytes boot rom (brom)
tc1130 data sheet 42 v0.3, 2003-09 address map table 2 defines the specific segment oriented address blocks of the tc1130 with its address range, size, and pmi/dmi access view. table 3 shows the block address map of the segment 15 which in cludes on-chip peri pheral units and ports. table 2 tc1130 block address map seg- ment address range size description dmi acc. pmi acc. 0 ? 7 0000 0000 h ? 7fff ffff h 2 gb mmu space via fpi via fpi c a c h e d 8 8000 0000 h ? 8fff ffff h 256 mb external memory space mapped from segment 10 via lmb via lmb 9 9000 0000 h ? 9fdf ffff h 256 mb reserved via fpi via fpi 10 a000 0000 h ? afbf ffff h 252 mb external memory space via lmb via lmb n o n- c a c h e d afc0 0000 h ? afc0 ffff h 64 kb dmu space afc1 0000 h ? afff ffff h ~4 mb reserved 11 b000 0000 h ? bfff ffff h 256 mb reserved via fpi via fpi 12 c000 0000 h ? c000 ffff h 64 kb dmu via lmb via lmb c a c h e d c001 0000 h ? cfff ffff h ~ 256 mb reserved
tc1130 data sheet 43 v0.3, 2003-09 13 d000 0000 h ? d000 7fff h 32 kb dmi local data ram (ldram) dmi local via lmb non-cached d000 8000 h ? d3ff ffff h ~ 64 mb reserved d400 0000 h ? d400 7fff h 32 kb pmi local code scratchpad ram (spram) via lmb pmi local d400 8000 h ? d7ff ffff h ~64 mb reserved d800 0000 h ? ddff ffff h 96 mb external memory space via lmb via lmb de00 0000 h ? deff ffff h 16 mb emulator memory space df00 0000 h ? dfff bfff h ~16 mb reserved ? ? dfff c000 h ? dfff ffff h 16 kb boot rom space via fpi via fpi 14 e000 0000 h ? e7ff ffff h 128 mb external memory space via lmb via lmb e800 0000 h ? e83f ffff h 4 mb reserved for mapped space for lower 4 mbyte of local memory in segment 12 (transformed by lfi bridge to c000 0000 h ? c03f ffff h ) ? ? e840 0000 h ? e84f ffff h 1 mb reserved for mapped space for lower 1 mbyte of local memory in segment 13 (transformed by lfi bridge to d000 0000 h ? d00f ffff h ) acces s only from fpi bus side of lfi access only from fpi bus side of lfi e850 0000 h ? e85f ffff h 1 mb reserved for mapped space for 1 mbyte of local memory in segment 13 (transformed by lfi bridge to d400 0000 h ? d40f ffff h ) e860 0000 h ? efff ffff h 122 mb reserved ? ? table 2 tc1130 block address map (cont?d) seg- ment address range size description dmi acc. pmi acc.
tc1130 data sheet 44 v0.3, 2003-09 15 f000 0000 h ? f00f ffff h 1 mb on-chip system peripherals & ports via fpi via fpi non-cached f010 0000 h ? f027 ffff h 1.5 mb peripherals on smif interface of dma controller f028 0000 h ? f200 00ff h ~29.5 mb reserved ? ? f200 0100 h ? f200 05ff h 1280 bytes ethernet controller registers via fpi via fpi f200 0600 h ? f7e0 feff h ~94 mb reserved ? ? f7e0 ff00 h ? f7e0 ffff h 256 bytes cpu slave interface registers (cps) via lmb via lmb f7e1 0000 h ? f7e1 ffff h 64 kb core sfrs f7e2 0000 h ? f7ff ffff h ~1.8 mb reserved ? ? f800 0000 h ? f87f ffff h 8 mb lmb peripheral space (ebu and local memory dmu control registers) via lmb via lmb f880 0000 h ? ffff ffff h 120 mb reserved ? ? table 3 block address map of segment 15 symbol description address range size system peripheral bus (spb) scu system control unit (incl. wdt) f000 0000 h - f000 00ff h 256 bytes sbcu fpi bus control unit f000 0100 h - f000 01ff h 256 bytes stm system timer f000 0200 h - f000 02ff h 256 bytes ocds on-chip debug support (cerberus) f000 0300 h - f000 03ff h 256 bytes ? reserved f000 0400 h - f000 04ff h 256 bytes ? reserved f000 0500 h - f000 05ff h 256 bytes table 2 tc1130 block address map (cont?d) seg- ment address range size description dmi acc. pmi acc.
tc1130 data sheet 45 v0.3, 2003-09 gptu general purpose timer unit f000 0600 h - f000 06ff h 256 bytes ? reserved f000 0700 h - f000 07ff h 256 bytes ? reserved f000 0800 h - f000 08ff h 256 bytes ? reserved f000 0900 h - f000 09ff h 256 bytes ? reserved f000 0a00 h - f0000aff h 256 bytes ? reserved f000 0b00 h - f0000bff h 256 bytes p0 port 0 f000 0c00 h -f0000cff h 256 bytes p1 port 1 f000 0d00 h -f0000dff h 256 bytes p2 port 2 f000 0e00 h -f000 0eff h 256 bytes p3 port 3 f000 0f00 h - f000 0fff h 256 bytes p4 port 4 f000 1000 h - f000 10ff h 256 bytes ? reserved f000 1100 h - f000 11ff h 256 bytes ? reserved f000 1200 h - f000 12ff h 256 bytes ? reserved f000 1300 h - f000 13ff h 256 bytes ? reserved f000 1400 h - f000 14ff h 256 bytes ? reserved f000 1500 h - f000 15ff h 256 bytes ? reserved f000 1600 h - f000 16ff h 256 bytes ? reserved f000 1700 h - f000 17ff h 256 bytes ? reserved f000 1800 h - f000 18ff h 256 bytes ? reserved f000 1900 h - f000 19ff h 256 bytes ccu60 capture/compare unit 0 f000 2000 h - f000 20ff h 256 bytes ccu61 capture/compare unit 1 f000 2100 h - f000 21ff h 256 bytes ? reserved f000 2200 h - f000 3bff h ? dma direct memory access controller f000 3c00 h - f0003eff h 3 256 bytes ? reserved f000 3f00 h - f000 3fff h ? can multican controller f000 4000 h - f000 5fff h 8 kbytes ? reserved f000 6000 h - f00e1fff h ? usb usb ram based registers f00e 2000 h - f00e 219f h 416 bytes usb usb ram f00e 21a0 h - f00e 27ff h 1.6 kbytes usb usb registers f00e 2800 h - f00e 28ff h 256 bytes table 3 block address ma p of segment 15(cont?d) symbol description address range size
tc1130 data sheet 46 v0.3, 2003-09 ? reserved f00e 2900 h - f00f ffff h ? units on smif interface of dma controller ? reserved f010 0000 h - f010 00ff h 256 byte ssc0 synchronous serial interface 0 f010 0100 h - f010 01ff h 256 byte ssc1 synchronous serial interface 1 f010 0200 h - f010 02ff h 256 byte asc0 async./sync. serial interface 0 f010 0300 h - f010 03ff h 256 byte asc1 async./sync. serial interface 1 f010 0400 h - f010 04ff h 256 byte asc2 async./sync. serial interface 2 f010 0500 h - f010 05ff h 256 byte i2c inter ic f010 0600 h - f010 06ff h 256 byte ? reserved f010 0700 h - f010bfff h ? mli0 multi link in terface 0 f010 c000 h -f010c0ff h 256 bytes mli1 multi link in terface 1 f010 c100 h -f010c1ff h 256 bytes mchk memory checker f010 c200 h -f010c2ff h 256 bytes ? reserved f010 c300 h -f01d ffff h ? mli0_ sp0 mli0 small transfer window 0 f01e 0000 h - f01e 1fff h 8 kbytes mli0_ sp1 mli0 small transfer window 1 f01e 2000 h - f01e 3fff h 8 kbytes mli0_ sp2 mli0 small transfer window 2 f01e 4000 h - f01e 5fff h 8 kbytes mli0_ sp3 mli0 small transfer window 3 f01e 6000 h - f01e 7fff h 8 kbytes mli1_ sp0 mli1 small transfer window 0 f01e 8000 h - f01e 9fff h 8 kbytes mli1_ sp1 mli1 small transfer window 1 f01e a000 h - f01e bfff h 8 kbytes mli1_ sp2 mli1 small transfer window 2 f01e c000 h - f01e dfff h 8 kbytes mli1_ sp3 mli1 small transfer window 3 f01e e000 h - f01e ffff h 8 kbytes ? reserved f01f 0000 h - f01f ffff h ? mli0_ lp0 mli0 large transfer window 0 f020 0000 h - f020 ffff h 64 k bytes table 3 block address ma p of segment 15(cont?d) symbol description address range size
tc1130 data sheet 47 v0.3, 2003-09 mli0_ lp1 mli0 large transfer window 1 f021 0000 h - f021 ffff h 64 k bytes mli0_ lp2 mli0 large transfer window 2 f022 0000 h - f022 ffff h 64 k bytes mli0_ lp3 mli0 large transfer window 3 f023 0000 h - f023 ffff h 64 k bytes mli1_ lp0 mli1 large transfer window 0 f024 0000 h - f024 ffff h 64 k bytes mli1_ lp1 mli1 large transfer window 1 f025 0000 h - f025 ffff h 64 k bytes mli1_ lp2 mli1 large transfer window 2 f026 0000 h - f026 ffff h 64 k bytes mli1_ lp3 mli1 large transfer window 3 f027 0000 h - f027 ffff h 64 k bytes ? reserved f028 0000 h - f200 00ff h ? ecu ethernet controller unit f200 0100 h - f200 05ff h 1280bytes ? reserved f200 0600 h - f7e0feff h ? cpu (part of system peripheral bus) cpu sfrs cpu slave interface f7e0 ff00 h -f7e0ffff h 256 bytes reserved f7e1 0000 h ?f7e17fff h ? mmu f7e1 8000 h ?f7e180ff h 256 bytes reserved f7e1 8100 h -f7e1bfff h ? memory protection registers f7e1 c000 h -f7e1efff h 12k bytes reserved f7e1 f000 h - f7e1fcff h ? core debug register (ocds) f7e1 fd00 h -f7e1fdff h 256 bytes core special function registers (csfrs) f7e1 fe00 h -f7e1feff h 256 bytes general purpose regist er (gprs) f7e1 ff00 h -f7e1 ffff h 256 bytes ? reserved f7e2 0000 h -f7ffffff h ? local memory buses (lmb) ebu external bus interface unit f800 0000 h - f800 03ff h 1kbytes table 3 block address ma p of segment 15(cont?d) symbol description address range size
tc1130 data sheet 48 v0.3, 2003-09 memory protection system the tc1130 memory protection system spec ifies the addressable range and read/write permissions of memory segments available to the currently executing task. the memory protection system controls the position and rang e of addressable segments in memory. it also controls the kinds of read and write operations allowed within addressable memory segments. any illegal memory acce ss is detected by the memory protection hardware, which then invokes the appropriate trap service ro utine (tsr) to handle the error. thus, the memory protec tion system protects critical system functions against both software and hardware errors. the memory protecti on hardware can also generate signals to the debug unit to facilitate tracing illegal memory accesses. in tc1130, tricore supports two address spaces: the virt ual address space and the physical address space. both address space are 4gb in size and divided into 16 segments with each segment be ing 256mb. the upper 4 bits of the 32-bit address are used to identify the segment. virtual segments are number ed 0 - 15. but a virtual address is always translated into a physical addr ess before accessing memory. the virtual address is translated into a physical addr ess using one of two translation mechanisms: (a) direct translation, and (b ) page table entry (pte) based translation. if the virtual address belongs to the upper ha lf of the virtual address sp ace then the virt ual address is directly used as the physical add ress (direct translation). if the virtual addr ess belongs to the lower half of the address space, then th e virtual address is us ed directly as the physical address if the proce ssor is operating in physical mode (direct translation) or translated using a page table entry if the processor is operating in virtual mode (pte translation). these are managed by memory managem ent unit (mmu) memory protection is enforced using separate mechanisms for the two translation paths. protection for dir ect translation memory protection for addresse s that undergo direct transl ation is enforced using the range based protection that has been used in the previous genera tion of the tricore architecture. the range based protection mechanism provides support for protecting dmu data memory unit f800 0400 h - f800 04ff h 256 bytes - reserved f800 0500 h -f87f fbff h ? dmi data memory interface unit f87f fc00 h -f87ffcff h 256 bytes pmi program memory in terface unit f87f fd00 h -f87ffdff h 256 bytes lbcu local memory bus co ntrol unit f87f fe00 h - f87f feff h 256 bytes lfi lmb to fpi bus bridge f87f ff00 h - f87f ffff h 256 bytes ? reserved f880 0000 h - ffff ffff h ? table 3 block address ma p of segment 15(cont?d) symbol description address range size
tc1130 data sheet 49 v0.3, 2003-09 memory ranges from unautho rized read, write, or inst ruction fetch accesses. the tricore architecture provides up to four prot ection register sets with the psw.prs field controlling the selection of the protection register set. because the tc1130 uses a harvard-style memory architecture, each me mory protection register set is broken down into a data protection register set and a code protection register set. each data protection register set can specify up to four address ranges to receive particular protection modes. each code protection re gister set can specify up to two address ranges to receive partic ular protection modes. each of the data protecti on register sets and code protection register sets determines the range and protec tion modes for a separate memory area. each contains register pairs which determi ne the address ra nge (the data segment protection registers and code segment pr otection registers) and on e register (data protection mode register) which determines the me mory access modes wh ich apply to the specified range. protection for pte based translation memory protection for addre sses that undergo pte based tr anslation is enforced using the pte used for the address translation. the pte provides supp ort for protecting a process from unauthorized read, write, or in struction fetches by other processes. the pte has the following bits that are provided for th e purpose of protection: l xe (execute enable) enables in struction fetch to the page. l we (write enable) enables data writes to the page. l re (read enable) enables data reads from the page. furthermore, user-0 accesses to virtual ad dresses in the upper half of the virtual address space are disallowed when operating in virtual mo de. in physical mode, user- 0 accesses are disallowed only to segments 14 and 15. any user-0 access to a virtual address that is restri cted to user-1 or super-visor mo de will cause a virtual address protection (vap) trap in both the physical and virtual modes. memory checker the memory checker module (mchk) al lows to check the data consistency of memories. it uses dma moves to read from the selected a ddress area and to write the value read in a memory checke r input register (the moves should be 32 bit moves). a polynomial checksum calculation is done with each write oper ation to the memory checker input register
tc1130 data sheet 50 v0.3, 2003-09 on-chip bus system the tc1130 includes two bus systems: ? local memory bus (lmb) ? on-chip fpi bus (fpi) the lmb-to-fpi (lfi) br idge interconnects the fpi bus and lmb bus. local memory bus (lmb) the local memory bus interconnects the memo ry units and function al units, such as cpu and dmu. the main target of the lmb bus is to suppor t devices with fast response times, optimized for speed. this allows the dmi and pmi fast access to local memory and reduces load on the fpi bus. the tricore system itself is loca ted on lmb bus. via external bus unit, it interconnects tc 1130 and external components. the local memory bus is a synchronous, pi pelined, split bus with variable block size transfer support. it supports 8, 16, 32 & 64 bits single beat tr ansactions and variable length 64 bits bl ock transfers. key features the lmb provides the following features: synchronous, pipelined, multi-mast er, 64-bit high performance bus optimized for high spee d and high performance 32 bit address, 64 bit data busses support split transactions support variable bl ock size transfer burst mode read/write to memories connect caches and on-c hip memory and fpi bus slave controlled wait state insertion support locked transact ion (read-modify-write)
tc1130 data sheet 51 v0.3, 2003-09 on-chip fpi bus the fpi bus interconnects the functional units of the tc11 30, such as the dma and on- chip peripheral compo nents. the fpi bus is designed to be quick to acquire by on-chip functional units, and quick to transfer data. the low setu p overhead of the fpi bus access protocol guarantees fast fpi bus acquisition, which is required for time-critical applications.the fpi bus is designed to sust ain high transfer rates. for example, a peak transfer rate of up to 800 mbytes/s can be achieved with a 100 mhz bus clock and 32- bit data bus. multiple data tr ansfers per bus arbitr ation cycle allow the fpi bus to operate at close to its peak bandwidth. features supports multiple bus masters supports demultiplexed address/data operation address bus up to 32 bits and data buses are 64 bits wide data transfer types include 8-, 16-, 32- and 64 bit sizes supports burst transfer single- and multiple-data tran sfers per bus acquisition cycle designed to minimize em i and power consumption controlled by an bus control unit (bcu) ? arbitration of fpi bus master requests ? handling of bus error. lfi the lmb-to-fpi interface (lfi) block provides the circuitry to inte rface (bridge) the fpi bus to the local memory bus (lmb). lfi features compatible with th e fpi 3.2 and lmb bus specification v2.4 supports burst/single transa ctions, from fpi to lmb. supports burst/single transa ctions, from lmb to fpi high efficiency and performance: ? fastest access across the bridge takes three cycles, using a bypass. ? there are no dead cycles on arbitration. acts as the default master on fpi side. supports abort, error a nd retry condition s on both sides of the bridge. supports fpi?s clock the same, or half, as the lmb?s clock frequency. lmb clock is shut when no transactions are issue to lfi from both buses and none are in process in the lfi to mi nimize the power consumption.
tc1130 data sheet 52 v0.3, 2003-09 lmb external bus unit the lmb external bus control unit (ebu) of the tc11 30 is the interface between external resources, like memories and peri pheral units, and the internal resources connected to on-chip buse s if enabled. the basic structur e and external interconnections of the ebu are shown in figure 14 . figure 14 ebu struct ure and interfaces mcb04941_mod ebu_lmb ad[31:0] bc[3:0] a[23:0] rd rd/wr wait cscomb adv ale ras cs[3:0] bfclko cas cke mr/w p1.15/rmw p0.5/hold bfclki baa 32 4 24 4 lmb pmi dmi lfi mmu tri core fpi to peripherals sdclki sdclko port 0 control p0.6/hlda p0.4/breq port 1 control p2.0/csemu port 2 control
tc1130 data sheet 53 v0.3, 2003-09 the ebu is mainly used for the operation that masters on lm b bus access external memories through ebu. the ebu controls all transactions required for this operations and in particular handles the arbitration of the extern al bus between multi-masters. the types of external resour ces accessed by the ebu are: intel style peripherals (separate rd and wr signals) roms, eproms static rams pc 100 sdrams (burst read/write ca pacity / multi-bank/page support) specific types of burst mode flashes (intel 28f800f3/28f160f3, amd 29bl162) special support for extern al emulator/debug hardware features support local memory bus (lmb 64-bit) support external bus frequency: lmb frequency =1:1 or 1:2 highly programmable access parameters support intel-style peripherals/devices support pc 100 sdram (b urst access, multibanki ng, precharge, refresh) support 16-and 32-bit sdram data bus and 64,128 and 256mbit devices support burst flash (intel 28f800f3/160f3,amd 29bl162) support multiplexed access (address &data on the same bus) when pc 100 sdram is not implemented support data buffering: code pr efetch buffer, r ead/write buffer. external master arbitration compatible to c166 and other tricore devices 4 programmable address region s (1 dedicated for emulator) support little-endian signal for controlli ng data flow of slow-memory buffer
tc1130 data sheet 54 v0.3, 2003-09 direct memory access (dma) the direct memory access controller ex ecutes dma transactions from a source address location to a destinat ion address location, without in tervention of the cpu. one dma transaction is controlled by one dma channel. each dma channel has assigned its own channel register set. the total of 8 channels ar e provided by one dma sub-block. the dma module is connected to 3 bus interf aces in tc1130, the flexible peripheral interconnect bus (fpi), the dma bus and the mi cro link bus. it ca n do transfers on each of the buses as well as between the buses. in addition it bridges accesse s from the flexible peripher al interconnect bus to the peripherals on the dma bus, allowing easy access to these peripherals by cpu. clock control, address decoding, dma request wiring, and dma interrupt service request control are implementation specific and ma naged outside the dma controller kernel. features 8 independent dma channels ? up to 8 selectable reques t inputs pe r dma channel ? programmable priority of dma channels within a dm a sub-block (2 levels) ? software and hardware dma request generation ? hardware requests by selected peripherals and external inputs programmable priority of the dm a sub-block on the bus interfaces buffer capability for move actions on the buses (min. 1 move per bus is buffered). individually programmable operati on modes for each dma channel ? single mode: stops and disables dma ch annel after a predef ined number of dma transfers ? continuous mode: dma channel remains enabled after a predefined number of dma transfers; dma transaction can be repeated. ? programmable address modification full 32-bit addressing capability of each dma channel ? 4 gbyte address range ? support of circular buffer addressing mode programmable data width of a dma tr ansaction: 8-bit, 16-bit, or 32-bit micro link supported register set for each dma channel ? source and destination address register ? channel control and status register ? transfer count register flexible interrupt g eneration (the service request no de logic for th e mli channels is also implemented in the dma module) all buses/interfaces connec ted to the dma modu le must work at the same frequency. read/write requests of the system bus side to the remote peripher als are bridged to the dma bus (only the dma is master on the dma bus)
tc1130 data sheet 55 v0.3, 2003-09 the basic structure and external inte rconnections of the dma are shown in figure 15 figure 15 dma controller structure and interconnections dma request wiring matri x interrupt control tc1130_dmaimplementation cl ock control address decoder dma controller arbiter/ switch control switch bus interface 0 m/s bus interface 2 smif sr [3:0] f dma asc0 2 2 asc1 2 2 asc2 ssc0 2 1 ssc1 4 ccu60 4 4 scu (ext.trg) mli1 dma interrupt control unit 4 multican to fpi bus mli0 1 i2c ccu61 4 sr [15:12] 1 channel 00-07 registers dma sub-block 0 request assignment and priorisation uni t 0 8 transaction control engine 8 1 usb bus interface 1 m/s asc0 asc1 asc2 ssc0 ssc1 iic dma bus mli0 mli1 mem check dma bus
tc1130 data sheet 56 v0.3, 2003-09 system timer the stm within the tc1130 is designed for global system timing appl ications requiring both high precision and long range. th e stm provides the following features: free-running 56-bit counter all 56 bits can be read synchronously different 32-bit portions of the 56 -bit counter can be read synchronously flexible interrupt generation on partial stm content compare match driven by clock f stm after reset (default after reset is f stm = f sys = 150 mhz) counting starts automatica lly after a reset operation stm is reset under fo llowing reset causes: ? wake-up reset (pmg_con.dsrw must be set) ? software reset (rst_req.rrstm must be set) ? power-on reset stm (and clock divider) is not reset at watchdog reset and ha rdware reset (hdrst = 0) the stm is an upward counter, runn ing with the syst em clock frequency f sys (after reset f stm = f sys ). it is enabled per defau lt after reset, and immedi ately starts counting up. other than via reset, it is no possible to affect the contents of the ti mer during normal operation of the application, it can only be read, but not written to. dep ending on the implementation of the clock control of the stm, the timer can opti onally be disabled or suspended for power-saving and debugging purposes via a clock control register the maximum clock period is 2 56 / f stm . at f stm = 150 mhz (maximum), for example, the stm counts 15.2 years before overflowing. thus, it is capable of continuously timing the entire expected product life-time of a system without overflowing.
tc1130 data sheet 57 v0.3, 2003-09 figure 16 block diagram of the stm module stm module 00 h cap tim6 tim5 tim4 tim3 tim2 tim1 tim0 00 h 55 47 39 31 23 15 7 56-bit system timer address decoder clock control enable / disable f stm mca04795_mod 31 23 15 7 compare register cmp0 interrupt control compare register cmp1 stmir1 stmir0 porst 0 0 31 23 15 7 0
tc1130 data sheet 58 v0.3, 2003-09 watchdog timer the watchdog timer (wdt) provides a highly reliable and secure way to detect and recover from software or ha rdware failure. the wdt hel ps to abort an accidental malfunction of the tc1130 in a user-specifi ed time period. when enabled, the wdt will cause the tc1130 system to be reset if t he wdt is not serviced within a user- programmable time period. the cpu must service the wdt with in this time interval to prevent the wdt from causing a tc1130 system reset. hence, rout ine service of the wdt confirms that the system is functioning properly. in addition to this standa rd ?watchdog? function, the wdt incorporates the endinit feature and monitors its modi fications. a system-wide line is connected to the endinit bit implemented in a wdt control register, serv ing as an addi tional write-protection for critical registers (besides supervisor mode pr otection). registers pr otected via this line can only be modified when supervisor mode is active and bit endinit = 0. a further enhancement in th e tc1130?s watchdog time r is its reset prewarning operation. instead of immedi ately resetting the device on the detection of an error, as known from standard watchdogs, the wdt first issues an non-maskable interrupt (nmi) to the cpu before finally resetti ng the device at a specified time period later. this gives the cpu a chance to save syst em state to memory for late r examination of the cause of the malfunction, an important aid in debugging. features 16-bit watchdog counter selectable input frequency: f sys /256 or f sys /16384 16-bit user-definable reload value for normal watchdog operation, fixed reload value for time-out a nd prewarning modes incorporation of the endinit bit an d monitoring of its modifications sophisticated password acce ss mechanism with fixed a nd user-definable password fields proper access always requires two wr ite accesses. the time between the two accesses is monitored by the wdt and limited. access error detection: invalid password (d uring first access) or invalid guard bits (during second access) trigger the watchd og reset generation. overflow error detection: an overflow of the counter tr iggers the watchdog reset generation. watchdog function can be disabled; acce ss protection and endi nit monitor function remain enabled. double reset detection: if a watchdog in duced reset occurs twice without a proper access to its control register in between, a severe system malfun ction is assumed and the tc1130 is held in reset un til a power-on reset. this prev ents the device from being periodically reset if, for instance, connect ion to the external memory has been lost such that even syste m initialization coul d not be performed.
tc1130 data sheet 59 v0.3, 2003-09 important debugging support is provided through the re set prewarning operation by first issuing an nmi to the cp u before finally resetting the device after a certain period of time. system control unit the system control unit (s cu) of the tc1130 handles the system control tasks. all these system functions are tightly coupled, thus, they are conveni ently handled by one unit, the scu. the syst em tasks of the scu are: pll control ? pll_clc clock control register reset control ? generation of all in ternal reset signals ? generation of external hdrst reset signal boot scheme ? hardware booting scheme ? software booting scheme power management control ? enabling of severa l power-down modes ? control of the pll in power-down modes watchdog timer ocds2 trace port control device identification registers
tc1130 data sheet 60 v0.3, 2003-09 interrupt system an interrupt request can be serviced by the cpu which is called ?service provider?. interrupt requests are referred as ?s ervice requests? in this document. each peripheral in the tc11 30 can generate service requ ests. additionally, the bus control unit, the debug unit, the dma controller and even the cpu itself can generate service requests to the serv ice provider. as shown in figure 17 , each unit that can generate service requests is connected to one or multiple se rvice request nodes (srn). each srn contains a service request control register mod_srcx, where ?mod? is the identifier of the service requesti ng unit and ?x? an optional index. the srns are connected to the interrupt control unit (icu) via the cp u interrupt arbitration bus. the icu arbitrates service requests for the cp u and administers the interrupt arbitration bus. units which can generate service requests are: ? asynchronous/synchronous serial inte rfaces (asc0 & asc1 & asc2) with 4 srns each ? high-speed synchronous serial interf aces (ssc0 & ssc1) with 3 srns each ? inter ic interfac e (iic) with 3 srns ? universal serial bu s (usb) with 8 srns ? micro link interface mli0 with 4 srns and mli1 with 2 srns ? general purpose timer un it (gptu) with 8 srns ? capture/compare unit (ccu60 & ccu61) with 4 srns each ? multican (can) with 16 srns ? ethernet controller with 9 srns ? external interrupts with 4 srns ? direct memory access cont roller (dma) with 4 srns ? dma bus with 1 srn ? system timer (stm) with 2 srns ? bus control units (sbcu and lbcu) with 1 srn each ? peripheral control processor (pcp) with 12 srns ? central processing unit (cpu) with 4 srns ? floating point unit (fpu) with 1 srn ? debug unit (ocds) with 1 srn the cpu can make service reque sts directly to itself (via the icu). the cpu service request nodes are activa ted through software.
tc1130 data sheet 61 v0.3, 2003-09 figure 17 block diagram of th e tc1130 interrupt system service req. nodes service req. nodes service requestors interrupt system cpu interrupt arbitration bus service requestors 4 srns 4 asc0 4 4 srns 4 asc1 4 4 srns 4 asc2 4 3 srns 3 ssc0 3 4 srns 4 mli0 4 3 srns 3 ssc1 3 2 srns 2 mli1 2 16 srns 16 multican 16 8 srns 8 usb 8 9 srns 9 ethernet 8 srns 8 gptu 8 2 srns 2 stm 2 1 srn 1 fpu 1 4 srns dma 4 4 1 srn sbcu 1 1 1 srn lbcu 1 1 4 srns ccu61 4 4 4 srns ccu60 4 4 4 srn ext. int. 4 4 3 srns iic 3 3 service req. nodes 4 4 srns 4 cpu interrupt control unit interrupt service providers int. req. pipn cpu ccpn int. ack. software interrupts icu 1 srn 1 ocds 1 9 1 srn 1 dma bus 1
tc1130 data sheet 62 v0.3, 2003-09 boot options the tc1130 booting schemes provides a numbe r of different boot opt ions for the start of code execution. table 4 shows the boot opti ons available in th e tc1130. table 4 boot selections brkin 1) 1) this input signal is active low. tm 1) hwcfg [2:0] type of boot pc start value (user entry) 11000 bootstrap loader . serial boot fr om asc to pmi scratchpad, run loaded program dfff fffc h 2) (d400 0000 h ) 2) this is the bootrom entry address; the star t address of user program in parentheses 001 bootstrap loader . serial boot from can to pmi scratchpad, run loaded program dfff fffc h 2) (d400 0000 h ) 010 bootstrap loader . serial boot fr om ssc to pmi scratchpad, run loaded program dfff fffc h 2) (d400 0000 h ) 011 external memory, ebu as master dfff fffc h 2) (a000 0000 h ) 100 external memory, ebu as slave dfff fffc h 2) (a000 0000 h ) 101 reserved ---- 110 pmi scratchpad d400 0000 h 111 reserved (stop) ---- 0 1 000 tristate chip ---- 001 go to external emulator space dffffffc h 2) (de00 0000 h ) 010-111 reserved (stop) ---- 0 0 000-111 reserved (stop) ----
tc1130 data sheet 63 v0.3, 2003-09 power management system the tc1130 power mana gement system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. there are three power management modes: run mode idle mode deep sleep mode table 5 describes these features of th e power management modes. besides these explicit software-control led power-saving modes, tc1130 supports automatic power-saving in that operating units, which are curre ntly not required or idle, are shut off automatica lly until their operati on is required again. table 5 power manageme nt mode summary mode description run the system is fu lly operational. al l clocks and periphera ls are enabled, as determined by software. idle the cpu clock is disabled, waiting fo r a condition to re turn it to run mode. idle mode can be entered by software wh en the processor has no active tasks to perform. all periphe rals remain powered and clocked. processor memory is accessible to peripherals. a rese t, watchdog timer event, a falling edge on the nmi pin, or any enabled interrupt event will return the system to run mode. deep sleep the system clock is shut off; only an external signal will restart the system. entering this stat e requires an orderly shut-down controlled by the power management state machine (pmsm).
tc1130 data sheet 64 v0.3, 2003-09 on-chip debug support the on-chip debug support of the tc1130 consists of the follo wing building blocks: ocds l1 module of tricore ocds l2 interface of tricore ocds l1 module in the bcu of the fpi bus ocds l1 facilities within the dma ocds l2 interface of dma ocds system control unit (oscu) multi core break switch (mcbs) jtag based debug inte rface (cerberus jdi) suspend functional ity of peripherals features tricore l1 ocds: ? hardware event generation unit ? break by debug instruction or break signal ? full single-step support in hardware , possible also with software break ? access to memory, sfrs , etc. on the fly dma l1 ocds: ? output break re quest on errors ? suspending of pre- selected channels level 2 trace port with 16 pins that outputs either tricore, or dma trace ocds system control unit (cerberus oscu) ? minimum number of pins r equired (no ocds enable pin) ? hardware allows hot attach of a debugger to a running system ? system is secure (can be locked from internal) multi core break switch (cerberus mcbs): ? tricore, dma, break pins, and bcus as break sources ? tricore as break targets; other parts can in addi tion be suspended ? synchronous stop and restart of the system ? break to suspend converter figure 18 shows a basic block diagr am of the building blocks.
tc1130 data sheet 65 v0.3, 2003-09 . figure 18 ocds support basic block diagram enab le , con tro l and reset tc1130 ocds block diagram bcu tricore ocds l1 ocds l2 ocds l1 dma fpi wat ch- dog timer periph.1 periph.n jdi debug i/f jtag controller mcbs break switch ce rb er u s oscu break and suspe nd si gna ls multiplexer dma l2 16 brkin tdi tdo brkout trst tms tck ocds2[15:0]
tc1130 data sheet 66 v0.3, 2003-09 clock generation unit the clock generation unit (cgu) allows a very flexible clock generation for tc1130. the power consumptio n is indirect proportional to the frequency, whereas the performance of the microcontroller is dire ct proportional to th e frequency. during user program execution the frequency can be programmed for an op timal ratio between performance and power cons umption. therefore the power consumption can be adapted to the actual application state. features the clock generation unit serves different purposes: pll feature for mult iplying clock source by different factors direct drive for direct clock put through comfortable state machine for secure switching between basic pll, direct or prescaler operation power down mode support usb clock source and control the clock generation unit in the tc1130, shown in figure 19 , consists of an oscillator circuit and one phase-locke d loop (pll). the pll c an convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. the pll also has fail-safe logic that detects degenerate external cl ock behavior such as abnormal frequency deviations or a to tal loss of the external clo ck. it can execute emergency actions if it losses the lo ck on the exte rnal clock. in general, the clock generation unit (cgu) is controlled through the system control unit (scu) module of the tc1130. figure 19 clock generation unit block diagram 1 > mca04940mod oscillator ci rcui t xtal1 xtal2 f osc phase detect. vco n di vi der pll f vco 1 0 1:1/1:2 divider f sys lock detector oscr pll_ lock ndiv [6:0] vco_ bypass kdiv [3:0] pll_ bypass system control unit scu register pll_clc mux mux k:1/k:2 divider vco_ sel[1:0] f cpu sys fsl clock generation unit cgu p di vi - der osc. run detect. pdiv [2:0] osc disc p4.0/ usbclk di vi der mux f usb register scu_con usbc ldiv usbc lsel register osc_con mosc ogc
tc1130 data sheet 67 v0.3, 2003-09 recommended oscillator circuits figure 20 oscillator circuitries for the main oscillator of the tc1130, the following exte rnal passive components are recommended: ? crystal: 0~40 mhz ? c1, c2: 10 pf a block capacitor between v ddosc3 and v ssosc , v ddosc and v ssosc is recommended, too. osc_cedar tc1130 oscillator v ddosc v ssosc c 1 4 - 40 mhz c 2 xtal1 xtal2 tc1130 oscillator v ddosc v ssosc xtal1 xtal2 external clock signal f osc f osc fundamental mode crystal v ddosc3 v ddosc3
tc1130 data sheet 68 v0.3, 2003-09 power supply the tc1130 provides an ingenio us power supply concept in order to improve the emi behavior as well as to minimize th e crosstalk within on-chip modules. figure 21 shows the tc1130?s power supply concep t, where certain logic modules are individually supplied wi th power. this concept improves the emi behavior by reduction of the noise cross coupling. figure 21 tc1130 power supply concept mcb04953mod dmu dmi pmi cpu & peripheral logic gpio ports (p0-p4) ebu ports osc v ddo sc3 (3.3v) v ss v ddo sc (1.5v) v ss v ddp (3.3 v) v ss v ss (1.5 v) v dd
tc1130 data sheet 69 v0.3, 2003-09 power sequencing during power-up reset pin porst has to be held active until both power supply voltages have reached at l east their minimum values. during the power-up time (rising of the supply voltages from 0 to their regular operating values) it has to be ens ured, that the core v dd power supply reache s its operating value first, and then the gpio v ddp power supply. during the rising time of the core voltage it must be ensure d that 0< v dd -v ddp <0.5 v. during power-down, the core and gpio power supplies v dd and v ddp respectively, have to be switched off comple tely until all capacitances are discharged to zero, before the next power-up. note: the state of the pins are undef ined when only the port voltage v ddp is switched on.
tc1130 data sheet 70 v0.3, 2003-09 identification register values table 6 tc1130 identi fication registers short name address value scu_id f000 0008 h 002c c001 h manid f000 0070 h 0000 1820 h chipid f000 0074 h 0000 8c01 h rtid f000 0078 h 0000 0000 h sbcu_id f000 0108 h 0000 6a0a h stm_id f000 0208 h 0000 c005 h jdp_id f000 0308 h 0000 6307 h gptu_id f000 0608 h 0001 c002 h ccu60_id f000 2008 h 0042 c004 h ccu61_id f000 2108 h 0042 c004 h dma_id f000 3c08 h 001a c011 h can_id f000 4008 h 002b c021 h usb_id f00e 2808 h 0000 4a00 h ssc0_id f010 0108 h 0000 4530 h ssc1_id f010 0208 h 0000 4530 h asc0_id f010 0308 h 0000 44e2 h asc1_id f010 0408 h 0000 44e2 h asc2_id f010 0508 h 0000 44e2 h iic_id f010 0608 h 0000 4604 h mli0_id f010 c008 h 0025 c004 h mli1_id f010 c108 h 0025 c004 h mchk_id f010 c208 h 001b c001 h cps_id f7e0 ff08 h 0015 c006 h mmu_id f7e1 8008 h 0009 c002 h cpu_id f7e1 fe18 h 000a c005 h ebu_id f800 0008 h 0014 c004 h dmu_id f800 0408 h 002d c001 h dmi_id f87f fc08 h 0008 c004 h pmi_id f87f fd08 h 000b c004 h
tc1130 data sheet 71 v0.3, 2003-09 lbcu_id f87f fe08 h 000f c005 h lfi_id f87f ff08 h 000c c005 h table 6 tc1130 identi fication registers short name address value
tc1130 data sheet 72 v0.3, 2003-09 absolute maximum rating targets note: stresses above those listed under ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods ma y affect device reliability. during absolute maximum ra ting overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absol ute maximum ratings. parameter symbol limit values unit notes min. max. ambient temperature t a -40 85 c under bias storage temperature t st -65 150 c? junction temperature t j -40 125 c under bias voltage at 1.5v power supply pins with respect to v ss 1) 1) applicable for v dd and v ddosc . v ddc -0.5 1.7 v ? voltage at 3.3v power supply pins with respect to v ss 2) 2) applicable for v ddp and v ddosc3 . the maximum voltage difference must not exceed 4.0v in any case (i.e. supply voltage = 4.0v and input voltage = -0.5v is not allowed). v ddp -0.5 4.0 v ? voltage on any pi n with respect to v ss 2) v in -0.5 4.0 v ? input current on any pin during overload condition i in -10 10 ma 3) 3) restricted life time: tbd absolute sum of all input currents during overload condition i in ? |100| ma 3) cpu & lmb bus frequency f sys ?150mhz? fpi bus frequency f fpi ?100mhz? power dissipation p d ?tbdw?
tc1130 data sheet 73 v0.3, 2003-09 operating condition the following operating conditions must no t be exceeded in orde r to ensure correct operation of the tc1130. all parameters specified in the fo llowing table refer to these operating conditions, un less otherwise noticed. parameter symbol limit values unit notes conditions min. max. digital supply voltage v ddc 1.43 1.58 v v ddp 3.14 3.47 v digital ground voltage v ss 0v? digital core supply current i dd 525 ma ambient temperature under bias t a -40 +85 c? cpu clock f sys ? 1) 1) the tc1130 uses a static design, so the minimum operati on frequency is 0 mhz. due to test time restriction no lower frequency boundary is tested, however. 150 mhz ? overload current i ov -1 1 ma 2)3) 2) overload conditions occur if the standard operating co nditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov > v ddp + 0.5 v or v ov < v ss - 0.5 v). the absolute sum of input overload currents on all digita l io pins may not exceed 50 ma . the supply voltage must remain within the specified limits. 3) not 100% tested, guaranteed by design and characterization. -3 3 duty cycle 25% short circuit current i sc -1 1 ma 4) -3 3 duty cycle 25% absolute sum of overload + short circuit currents | i ov |+ | i sc | ?|50|ma 3) |100| duty cycle 25% inactive device pin current (v dd =v ddp =0) i id -1 1 ma ? external load capacitance c l ?50pf esd strength 2000 ? v human body model (hbm)
tc1130 data sheet 74 v0.3, 2003-09 4) applicable for digital inputs. parameter interpretation the parameters listed on the fo llowing pages partly represen t the characteristics of the tc1130 and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design , they are marked in column ?symbol?: cc ( c ontroller c haracteristics): the logic of the tc1130 will provide signals with the respective timing characteristics. sr ( s ystem r equirement): the external system must prov ide signals with the respecti ve timing characteristics to the tc1130.
tc1130 data sheet 75 v0.3, 2003-09 dc characteristics dc-characteristics v ss = 0 v; t a = -40 c to +125 c parameter symbol limit va lues unit test condition min. max. gpio pins, dedicated pins and ebu pins input low voltage v il sr -0.3 0.8 v lvttl input high voltage v ih sr 2.0 v ddp + 0.3 v lvttl output low voltage v ol cc ? 0.4 v i ol = 2ma output high voltage v oh cc 2.4 ? v i oh = -2ma pull-up current 1) 1) the current is applicable to the pins, for wh ich a pull up has been specified. refer to table 1 . i pu x refers to the pull up current for type x in absolute values . |i pua | cc ? 149 a v in = 0v |i puc | cc ?7.2 a v in = 0v pull-down current 2) 2) the current is applicable to the pins, for which a pull down has been specified. refer to table 1 . i pd x refers to the pull down current for type x in absolute values . |i pda | cc ? 156 a v in = v ddp |i pdc | cc ? 15.7 a v in = v ddp input leakage current 3) 3) excluded following pins : nmi , trst , tck, tdi, tms, mii_ txclk, mii_ rxclk, mii_ mdio, ale, p2.1,hwcfg0, hwcfg1, hwcfg2, brkin, porst, hdrst. i oz1 cc ? 350 na 0 < v in < v ddp pin capacitance 4) 4) not 100% tested, guaranteed by design characterization. c io cc ? 10 pf f = 1 mhz t a = 25 c oscillator pins input low voltage at xtal1 v ilx sr 0 0.1 v input high voltage at xtal1 v ihx sr 1.4 1.5 v notes:
tc1130 data sheet 76 v0.3, 2003-09 usb interface table 8 full speed electr ical characteristic table 7 dc electrical characteristics parameter symbol limit values unit test conditions min. typ. max. supply voltage supply voltage extern v ddp 3.14 3.3 3.47 v supply voltage intern v dde 1.4 1.5 1.6 v input level differential input level 0.2 v | v (d+) - v (d-)| differential common mode range 0.8 2.5 v range of sensitivity single ended receiver threshold low < 0.8 high > 2.0 v output levels static output low < 0.3 v with 1.5 k ? to 3.6 v static output high 2.8 3.3 3.6 v with 15 k ? to ground leakage current hi_z state data line leakage -10 10 a0 < v in < 3.3v parameter symbol limit values unit test conditions min. typ. max. driver characteristics rise / fall time 4 20 ns capacitive load 50 pf rise / fall time matching 90 100 110 % capacitive load 50 pf crossover voltage of differential signals 1.3 2.0 v capacitive load 50 pf driver output impedance 28 44 ? steady state driver termination impedance 1.425 1.5 1.575 k ?
tc1130 data sheet 77 v0.3, 2003-09 figure 22 usb interface usb interface 22 ? 22 ? 1.5k ? r s r s d + d - v ddp v ddp v ddp
tc1130 data sheet 78 v0.3, 2003-09 iic pins each iic pin is an open drain output pin with different char acteristics than other pins. the related characteristics are gi ven in the following table note: no 5 v iic interface is supported with these pads. only voltages lower than 3.63 v must be applied to these pads. note: iic pins have no pu ll-up and pull-down devices. parameter symbol limit values unit test conditions min. max. output low voltage v ol cc -0.4 0.6 v 3 ma sink current 6 ma sink current input high voltage 1) 1) guaranteed by design characterization v ih sr 0.7v ddp v ddp +0.5 v - input low voltage 1) v il sr -0.5 0.3v ddp v-
tc1130 data sheet 79 v0.3, 2003-09 power supply current parameter symbol limit values unit test conditions typ. 1) 1) typical values are measured at 25c, cpu clock at xxx mhz and nominal supply voltage, i.e. 3.3v for v ddp , v ddosc3 and 1.5v for v dd , v ddosc . these currents are measured using a typical application pattern. the power consumption of modules can increase or decrease using other application programs. max. active mode supply current i dd 314 679 ma sum of i dds 2) 2) these power supply currents are defined as the sum of all currents at the v dd power supply lines: v dd + v ddp + v ddosc3 + v ddosc 153 345 ma i dd at v dd 3) 3) this measurement includes the tricore and logic power supply lines. 156 322 ma i dd at v ddp idle mode supply current i id 74 154 ma sum of i dds 2)4) 4) cpu is in idle state, input clock to all peripherals are enabled, 66 130 ma i dd at v dd 3)4) 615 ma i dd at v ddp 4) deep sleep mode supply current i ds 219 ma sum of i dds 2)5) 5) clock generation is di sabled at the source. 219 ma i dd at v dd 3)5) 3.6 58 a i dd at v ddp 5)
tc1130 data sheet 80 v0.3, 2003-09 ac characteristics note: the values in blue color are gotten from sta. power, pad and reset timing parameter symbol limit values unit min. max. min. vddp voltage to ensure defined pad states v ddppa cc xxxx ? v oscillator start-up time 1) 1) not measured, guaranteed by device characterization t oscs cc ? 30 ms minimum porst active time after power supplies are stable at operating levels t poa cc 50 ? ms h rst pulse width t hd cc 1024 cycles 2) 2) any hdrst activation is internally prolonged to 1024 fpi bus clock cycles f sys ports inactive afte r any reset active 3) 3) not measured, guaranteed by design characterization t pi cc ? 30 ns
tc1130 data sheet 81 v0.3, 2003-09 pll parameters phase locked loop (pll) when pll operation is configured ( pll_clc.lock = 1 ) the on-chip phase locked loop is enabled and provides the ma ster clock. the pll multiplies the input frequency by the factor f ( f mc = f osc f ) which results from th e input divider, the mu ltiplication factor (n factor) , and the output divider ( f = ndiv+1 / (pdiv+1 kdiv+1) ). the pll circuit synchronizes the master clock to the input clock. this sync hronization is done smoothly, i.e. the master clock frequenc y does not change abruptly. due to this adaptation to t he input clock the frequency of f mc is constantly adjusted so it is locked to f osc . the slight variation causes a jitter of f mc which also affects the duration of individual tcms. the timing listed in the ac characte ristics refers to tcps. because f cpu is derived from f mc , the timing must be calcul ated using the minimum tcp po ssible under the respective circumstances. the actual minimum value for tcp depends on the jitter of the pll. as the pll is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the rela tive deviation for periods of mo re than one tcp is lower than for one single tcp (see formula and figure 23 ). reset_beh 1) as programmed vddp porst hdrst pads pad- state undefined t pi vdd v ddppa v ddppa pad- state undefined 2) tri-state, pull device active t hd v ddpr osc t oscs 1) 2) 1) 2) 2) t poa t poa t hd
tc1130 data sheet 82 v0.3, 2003-09 this is especially important fo r bus cycles using waitstates and e.g. for the operation of timers, serial interfac es, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is negligible. the value of the accumulat ed pll jitter depends on the number of consecutive vco output cycles within the respec tive timeframe. the vco outp ut clock is divided by the output prescaler (k = kdiv +1) to generate the master clock signal f mc . therefore, the number of vco cycles ca n be represented as k n , where n is the number of consecutive f mc cycles (tcm). for a period of n tcm the accumulated pll jitter is defined by the corresponding deviation d n : d n [ns] = (1.5 + 6.32 n / f mc ); f mc in [mhz], n = number of consecutive tcms. so, for a period of 3 tcms @ 20 mhz and k = 12: d 3 = (1.5 + 6.32 3 / 20) = 2.448 ns. this formula is applicable for k n < 95. for longer periods the k n =95 value can be used. this steady value c an be approximated by: d n max [ns] = (1.5 + 600 / (k f mc )). figure 23 approximated accumulated pll jitter note: the bold lines indicate the minimum accumulated jitter which can be achieved by selecting the maximum possible output prescaler factor k. mcb04413_xc.vsd acc. jitter d n 8 6 ns 4 2 1 0 510 20 25 n 1 0 m h z k=5 2 0 m h z 4 0 m h z 7 5 3 15 k=6 k=12 k=15 k=8 k=10 1
tc1130 data sheet 83 v0.3, 2003-09 different frequency band s can be selected for the vco, so the operati on of the pll can be adjusted to a wide range of input and outpu t frequencies: table 9 vco bands for pll operation pll_clc.vcosel vco frequency range base frequency range 1) 1) base frequency range is the free running operation fre quency of the pll, when no input clock is available. 00 400 ... 500 mh z 250 ... 320 mhz 01 500 ... 600 mhz 300 ... 400 mhz 10 600 ... 700 mhz 350 ... 480 mhz 11 reserved 2) 2) this option can not be used.
tc1130 data sheet 84 v0.3, 2003-09 ac characteristics (operating conditions apply) figure 24 input/output wa veforms for ac tests - for gpio, dedicated and ebu pins 2.0v 0.8v test points 2.0v 0.8v 2.4v 0.4v ac inputs during testing are driven at 2.4v for a logic ?1? and 0.4v for a logic ?0?. timing measurements are made at v ihmin for a logic ?1? and v ilmax for a logic ?0?.
tc1130 data sheet 85 v0.3, 2003-09 input clock timing (operating conditions apply) figure 25 input clock timing parameter symbol limits unit min max oscillator clock frequency with pll f osc sr 4 40 mhz input clock frequency driving at xtal1 with pll f oscdd sr -40mhz input clock duty cycle ( t 1 / t 2 )sr4555% input clock at xtal1 t 1 0.5 v dd t 2 t oscdd v ihx v ilx
tc1130 data sheet 86 v0.3, 2003-09 port timing (operating conditions apply; c l = 50 pf) figure 26 port timing parameter symbol limits unit min max port data valid from trclk 1) 1) port data is output with respect to the fpi clock. the trclk is used as a reference here since the fpi clock is not available as an external pin and trclk is same frequency as cpu clock. port lines maintain its state for at least 2 cpu clocks. t 1 cc ? 13 ns trclk old state new state t 1 port lines fpi_clk
tc1130 data sheet 87 v0.3, 2003-09 timing for ebu_lmb clock outputs sdclko output clock timing (operating conditions apply; cl = 50 pf) bfclko output clock timing (operating conditions apply; c l = 50 pf) figure 27 ebu cloc k output timing parameter symbol limits unit min max sdclko period t 1 cc10??ns sdclko high time t 2 cc 4.5 ? ? ns sdclko low time t 3 cc 3 ? ? ns sdclko rise time t 4 cc ? ?2.5ns sdclko fall time t 5 cc ? ?2.5ns sdclko duty cycle t 2 /( t 2 + t 3 ) dc cc 45 50 55 % parameter symbol limit values unit min. typ. max. clock period t 1 cc20??ns bfclko high time t 2 cc9??ns bfclko low time t 3 cc9??ns bfclko rise time t 4 cc ? ? 3.5 ns bfclko fall time t 5 cc ? ? 2.5 ns bfclko duty cycle t 2 /( t 2 + t 3 ) 1) 1) this duty cycle is not applicable when bfcon.ex tclock equals to 10 (1/3 of lmbclk frequency) dc cc 45 50 55 % bfclko/ sdclko t 5 t 2 t 3 t 0.5 v dd
tc1130 data sheet 88 v0.3, 2003-09 timing for sdram access signals (operating conditions apply; c l = 50 pf 1) ) 1) if application conditions other than 50 pf capacitive load are used, then the proper correlation factor should be used for your specific application condition. for design team, the load should be set according to the system requirement. parameter symbol limits unit min max cke output valid ti me from sdclko t 1 cc ? 8.0 ns cke output hold ti me from sdclko t 2 cc 1.0 ? ns address output valid time from sdclko t 3 cc ? 8.0 ns address output hold time from sdclko t 4 cc 1.0 ? ns csx , ras , cas , rd/wr , bc(3:0) output valid time from sdclko t 5 cc ? 8.0 ns csx , ras , cas , rd/wr , bc(3:0) output hold time from sdclko t 6 cc 1.0 ? ns ad(31:0) output valid time from sdclko t 7 cc ? 8.0 ns ad(31:0) output hold time from sdclko t 8 cc 1.0 ? ns ad(31:0) input setu p time to sdclko t 9 sr 4.0 ? ns ad(31:0) input hold time from sdclko t 10 sr 3.0 ? ns
tc1130 data sheet 89 v0.3, 2003-09 figure 28 sdram access timing sdclko cke address row csx ras cas rd/wr bc[3:0] ad[31:0] t 1 t 3 t 5 t 5 t 4 t 6 t 5 t 5 t 6 t 9 column t 6 t 6 t 10 d(0) d(n) sdclko cke address row csx ras cas rd/wr bc[3:0] ad[31:0] t 1 t 3 t 5 t 5 t 4 t 6 t 5 t 7 column t 6 t 6 t 8 d(0) d(n) read access write access t 5 t 6 sdram_timing t 2 t 5 t 6
tc1130 data sheet 90 v0.3, 2003-09 timing for burst flash access signals operating conditions apply; c l = 50 pf) parameter symbol limits unit min max address output valid time from bfclko t 1 cc ? 11.0 ns address output hold time from bfclko t 2 cc 10.0 ? ns csx output valid time from bfclko t 3 cc ? 9.0 ns rd output valid time from bfclko t 4 cc ? 10.0 ns adv output valid time from bfclko t 5 cc ? 10.0 (7.0) ns adv output hold time from bfclko t 6 cc 3.0 (0.0) ? ns baa output valid time from bfclko t 7 cc ? 10.0 (7.0) ns baa output hold time from bfclko t 8 cc 3.0 ? ns ad(31:0) input setu p time to bfclko t 9 sr 5.0 ? ns ad(31:0) input hold time from bfclko t 10 sr 3.0 ? ns wait input setup time to bfclko t 11 sr 5.0 ? ns wait input hold time from bfclko t 12 sr 3.0 ? ns
tc1130 data sheet 91 v0.3, 2003-09 figure 29 burst flash access timing note: output delays are always referenced to bfclko. the reference clock for input characteristics depends on bit bfcon.fdbken. bfcon.fdbken = 0: bfclko is the input reference clock. bfcon.fdbken = 1: bfclki is the in put reference clock (ebulmb clock feedback enabled) bfclko address csx adv rd baa d[31:0] t 1 t 3 t 5 t 6 t 4 t 9 t 11 t 12 t 2 t 7 t 8 t 10 bf_timing address d(0) d(n-1) wait address phase(s) command delay phase(s) command phase(s) burst phase(s) burst phase(s) recovery phase new addr. phase(s)
tc1130 data sheet 92 v0.3, 2003-09 timing for demultiplexed access signals (operating conditions apply; c l = 50 pf) 1) 1) the purpose for characterization of asynchronous acce ss is to provide the performance of all of the signals to user. user can decide whether an extra cycle is neede d or not based on above par ameters to generate signals with correct timing sequence. it is us er?s responsibility to program the correct phase length according to the memory/peripheral device specification and ebu specification. parameter symbol limits unit min max ale, csx , rd/wr , rd , mr/w , bc(3:0) output valid time from output clock t 1 cc ? 3.2 ns ale, csx , rd/wr , rd , mr/w , bc(3:0) output hold time from output clock t 2 cc 0.0 ? ns address output valid ti me from output clock t 3 cc ? 3.5 ns address output hold ti me from output clock t 4 cc 0.0 ? ns wait input setup time to output clock t 7 sr 10.6 ? ns wait input hold time from output clock t 8 sr 0.0 ? ns ad(31:0) output valid ti me from output clock t 9 cc ? 2.6 ns ad(31:0) output hold ti me from output clock t 10 cc 0.0 ? ns ad(31:0) input setup ti me to output clock t 11 sr 1.3 ? ns ad(31:0) input hold time from output clock t 12 sr 0.9 ? ns rmw output valid time from output clock t 13 cc ? 6.3 ns rmw output hold time from output clock t 14 cc 1.3 ? ns adv width t 15 cc 10 ? ns ad(31:0) output hold time from rd/wr t 16 cc 0 ? ns
tc1130 data sheet 93 v0.3, 2003-09 figure 30 demultiplexed asynch ronous device access timing sdclko adv address address csx rd/wr mr/w cmdelay bc[3:0] ad[31:0] t 1 t 3 t 1 t 1 t 4 t 2 t 1 t 9 t 2 t 2 t 10 dataout read access write access t 5 t 6 demux_timing t 2 t 1 wait t 7 t 8 t 2 t 1 sdclko/ sdclki adv address address csx rd mr/w cmdelay bc[3:0] ad[31:0] t 1 t 3 t 1 t 1 t 4 t 2 t 1 t 11 t 2 t 2 t 12 datain t 5 t 6 t 2 t 2 wait t 7 t 8 t 1 rmw t 13 t 14 address phase(s) command delay phase(s) (int.) command delay phase(s) (ext.) command phase(s) data hold phase(s) recovery phase address phase(s) command delay phase(s) (int.) command delay phase(s) (ext.) command phase(s) recovery phase t 16 t 15 t 15
tc1130 data sheet 94 v0.3, 2003-09 timing for multiplexed access signals (operating conditions apply; c l = 50 pf) 1) 1) the purpose for characterization of asynchronous acce ss is to provide the performance of all of the signals to user. user can decide whether an extra cycle is neede d or not based on above par ameters to generate signals with correct timing sequence. it is us er?s responsibility to program the correct phase length according to the memory/peripheral device specification and ebu specification. parameter symbol limits unit min max ale, csx , rd/wr , rd , mr/w , bc(3:0) output valid time from output clock t 1 cc ? 3.2 ns ale, csx , rd/wr , rd , mr/w , bc(3:0) output hold time from output clock t 2 cc 0.0 ? ns ad(31:0) output valid ti me from output clock t 3 cc ? 2.6 ns ad(31:0) output hold ti me from output clock t 4 cc 0.0 ? ns ad(31:0) input setup ti me to output clock t 5 sr 1.4 ? ns ad(31:0) input hold time from output clock t 6 sr 0.8 ? ns wait input setup time to output clock t 9 sr 10.6 ? ns wait input hold time from output clock t 10 sr 0.0 ? ns rmw output valid time from output clock t 11 cc ? 6.3 ns rmw output hold time from output clock t 12 cc 1.3 ? ns adv width t 13 cc 10.0 ? ns ad(31:0) output hold time from rd/wr t 14 cc 0 ? ns
tc1130 data sheet 95 v0.3, 2003-09 figure 31 write access in multiplexed access sdclko adv ad[31:0] address csx rd/wr mr/w cmdelay bc[3:0] t 1 t 3 t 1 t 1 t 4 t 2 t 1 t 2 t 2 read access write access t 7 t 8 mux_timing t 2 t 1 wait t 9 t 10 t 2 t 1 sdclko/ sdclki adv ad[31:0] address csx rd mr/w cmdelay bc[3:0] t 1 t 3 t 1 t 1 1 t 4 t 2 t 1 t 5 t 2 t 2 t 7 t 8 t 2 t 2 wait t 9 t 10 t 1 rmw t 11 t 12 t 4 t 3 t 6 data data address phase(s) address hold phase(s) command delay phase(s) (int.) command delay phase(s) (ext.) command phase(s) data hold phase(s) recovery phase(s) t 13 t 14 address phase(s) address hold phase(s) command delay phase(s) (int.) command delay phase(s) (ext.) command phase(s) recovery phase(s) t 13
tc1130 data sheet 96 v0.3, 2003-09 timing for external bus arbitration signals (operating conditions apply; c l = 50 pf) parameter symbol limits unit min max hold input setup time to output clock t 1 sr 7.3 ? ns hold input hold time from output clock t 2 sr 0.0 ? ns hlda output valid time from output clock t 3 cc ? 6.2 ns hlda output hold time from output clock t 4 cc 1.0 ? ns hlda input setup time to output clock t 5 sr 7.4 ? ns hlda input hold time from output clock t 6 sr 0.0 ? ns breq output valid time from output clock t 7 cc ? 6.4 ns breq output hold time from output clock t 8 cc 1.0 ? ns csx drive from ebuclk t 9 cc ? 3.1 ns csx high-impedance from ebuclk t 10 cc ? 3.1 ns other signals high-i mpedance from ebuclk t 11 cc ? 3.2 ns other signals drive from ebuclk t 12 cc ? 3.2 ns
tc1130 data sheet 97 v0.3, 2003-09 figure 32 external bus arbitration timing sdclko hold hlda breq csx other signals t 1 t 3 t 7 t 9 t 4 t 10 t 12 t 8 participant mode arbiter mode arbitration_timing t 2 t 9 t 11 sdclko breq hlda hold csx other signals t 7 t 5 t 1 t 9 t 6 t 11 t 2 t 8 t 10 t 12
tc1130 data sheet 98 v0.3, 2003-09 timing for ethernet signals (operating conditions apply; c l = 50 pf) note: any other parameters which are not stated here , please refer to ansi/i eee std 802.3, section 22.3. parameter symbol limits unit min max etxclk period (10 mbps ethernet) t 1 sr 400.0 ? ns etxclk high time (10 mbps ethernet) t 2 sr 140 260 ns etxclk low time (10 mbps ethernet) t 3 sr 140 260 ns etxclk period (100 mbps ethernet) t 1 sr 40.0 ? ns etxclk high time (100 mbps ethernet) t 2 sr 14 26 ns etxclk low time ( 100 mbps ethernet) t 3 sr 14 26 ns erxclk period (10 mbps ethernet) t 1 sr 400.0 ? ns erxclk high time (10 mbps ethernet) t 2 sr 140 260 ns erxclk low time (10 mbps ethernet) t 3 sr 140 260 ns erxclk period (100 mbps ethernet) t 1 sr 40.0 ? ns erxclk high time (1 00 mbps ethernet) t 2 sr 14 26 ns erxclk low time (100 mbps ethernet) t 3 sr 14 26 ns erxd(3:0) input setup to erxclk t 4 sr 10.0 ? ns erxd(3:0) input ho ld from erxclk t 5 sr ? 10.0 ns erxdv input setup to erxclk t 4 sr 10.0 ? ns erxdv input hold from erxclk t 5 sr ? 10.0 ns erxer input se tup to erxclk t 4 sr 10.0 ? ns erxer input hold from erxclk t 5 sr ? 10.0 ns etxd(3:0) output valid from etxclk t 6 cc ? 25.0 ns etxen output valid from etxclk t 6 cc ? 25.0 ns etxer output valid from etxclk t 6 cc ? 25.0 ns emdc clock period t 7 cc 400.0 ? ns emdc high time t 8 cc 160 ? ns emdc low time t 9 cc 160 ? ns emdio input setup to em dc (sourced by sta) t 10 sr 10.0 ? ns emdio input hold from emdc (sourced by sta) t 11 sr ? 10.0 ns emdio output valid from emdc (sourced by phy) t 12 cc ? 300.0 ns
tc1130 data sheet 99 v0.3, 2003-09 figure 33 ethernet timing t 1 etxclk erxclk erxd(3:0) erxdv erxer t 4 t 5 valid data etxd(3:0) etxen etxer t 6 valid data t 7 emdc emdio (sourced by sta) t 10 t 11 valid data t 12 emdio (sourced by phy) valid data t 2 t 3 t 8 t 9
tc1130 data sheet 100 v0.3, 2003-09 ssc master mode timing (operating conditions apply; c l = 50 pf) figure 34 ssc master mode timing parameter symbol limit values unit min. max. sclk clock frequency 1 / t sclk cc - 25 mhz sclk clock high time t 1 cc 18 - ns sclk clock low time t 2 cc 18 - ns sclk clock rise time t 3 cc - 11 ns sclk clock fall time t 4 cc - 11 ns mtsr/slsox low/high from sclk edge t 5 cc - 2.0 ns mrst setup to sclk edge t 6 sr 7 -ns mrst hold from sclk edge t 7 sr 5 -ns (con.po,con.ph = 00 or 11) 0.9 v dd 0.1 v dd t 1 t 2 t sclk t 3 t 4 data valid data valid t 2 t 1 t 5 state n-1 state n state n+1 0.9 v dd 0.1 v dd t 3 t 4 t 6 t 7 sclk (con.po,con.ph = 01 or 10) sclk mtsr mrst slsox 1) t 5 1) the tr ansi ti on slsox i s based on the fol l owi ng setup: ssotc.trail = 0 and the fi r st sclk hi g h pul se i s i n the fi r st one of a tr ansmi ssi on.
tc1130 data sheet 101 v0.3, 2003-09 timing for mli interface (operating conditions apply; c l = 50 pf) parameter symbol limit values unit min. max. tclk/rclk clock period t 0 cc/sr 26.67 ? ns tclk high time t 1 cc 9 ? ns tclk low time t 2 cc 9 ? ns tclk rise time t 3 cc ? 3 ns tclk fall time t 4 cc ? 3 ns tdatax, tvalidx outputs delay from tclk t 5 cc 08 ns treadyx inputs setup to tclk t 6 sr tbd ? ns rdatax, rvalidx inputs setup to rclk t 7 sr 5.3 ?ns rdatax, rvalidx in puts hold from rclk t 8 sr tbd ? ns rreadyx outputs del ay hold rclk t 9 cc tbd tbd ns
tc1130 data sheet 102 v0.3, 2003-09 figure 35 mli interface timing note: the generation of rreadyx is in th e input clock domain of the receiver. the reception of txready is asynchronous to tclkx (inp ut synchronization with each edge of tclkx). meeting the setup time for tx ready guarantees recognition of the txready at a certain clock edge. tdatax tvalidx t 5 t 5 t 8 t 7 tclkx t 0 t 1 t 2 t 4 t 3 rdatax rvalidx rclkx t 0 t 1 t 2 t 6 treadyx t 6
tc1130 data sheet 103 v0.3, 2003-09 timing for jtag signals (operating conditions apply; c l = 50 pf) figure 36 tck clock timing parameter symbol limits unit min max tck clock period t tck cc 50 ? ns tck high time t 1 cc 10 ? ns tck low time t 2 cc 29 ? ns tck clock rise time t 3 cc ? 0.4 ns tck clock fall time t 4 cc ? 0.4 ns tck t 4 0.9 v dd t 3 t 1 0.1 v dd t 2 t tck 0.5 v dd
tc1130 data sheet 104 v0.3, 2003-09 figure 37 jtag timing parameter symbol limits unit min max tms setup to tck t 1 sr 7.85 ? ns tms hold to tck t 2 sr 3.0 ? ns tdi setup to tck t 1 sr 10.9 ? ns tdi hold to tck t 2 sr 3.0 ? ns tdo valid outpu t from tck t 3 cc ? 10.7 ns tdo high impedance to va lid output from tck t 4 cc ? 23.0 ns tdo valid output to high impedance from tck t 5 cc ? 26.0 ns tms tdi tck tdo t 1 t 2 t 1 t 2 t 4 t 3 t 5
tc1130 data sheet 105 v0.3, 2003-09 timing for ocds trace an d breakpoint signals (operating conditions apply; c l (trclk) = 25 pf, c l = 50 pf) figure 38 ocds trace signals timing parameter symbol limits unit min max brk_out valid from trclk t 1 cc ? 5.2 ns ocds2_status[4:0] valid from trclk t 1 cc 1.7 3.7 ns ocds2_indir_pc[7:0] valid from trclk t 1 cc 1.7 3.7 ns ocds2_brkpt[2:0] valid from trclk t 1 cc 1.7 3.7 ns cpu trace signals trclk t 1 old state new state t 1 note: cpu trace signals include brk_in , brk_out , ocds2_status[4:0] , ocds2_indir_pc[7:0] and ocds_brkpt[2:0] .
tc1130 data sheet 106 v0.3, 2003-09 timing for usb transceiver signals (operating conditions apply; c l = 50 pf) figure 39 ac testing: input, output waveforms parameter symbol limits unit min max full speed mode rise time t fr cc 4 20 ns full speed mode fall time t ff cc 4 20 ns t r 10% 90% 10% 90% t f rise_fall_usb.emf d - d +
tc1130 data sheet 107 v0.3, 2003-09 package outline figure 40 p-lbga-208-2 package plastic package, p- lbga-208-2 (smd) (low profile ball grid array package) you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products. dimensions in mm smd = surface mounted device
tc1130 data sheet 108 v0.3, 2003-09
http://www.infineon.com published by infineo n technologies ag infineon goes for business excellence ?business excellence means inte lligent approaches and clearly defined processes, wh ich are both constant ly under review and ultimately lead to go od operating results. better operating results and business excellence mean less idleness and wastefulness for al l of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.? dr. ulrich schumacher

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